MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this document
by MC68HC11C0TS/D
MC68HC11C0
Technical Summary
8-Bit Microcontroller
1 Introduction
The MC68HC11C0 high-performance microcontroller unit (MCU) is an enhanced member of the
M68HC11 family of microcontrollers. Excluding its new features, the MC68HC11C0 is very similar to
the MC68HC11E9 MCU. This device incorporates highly sophisticated on-chip peripheral functions
and, with a multiplexed expanded bus, is characterized by high speed and low power consumption. Its
fully static design allows this device to operate at frequencies from 3 MHz to dc.
The MC68HC11C0 has the ability to extend the address range of the M68HC11 CPU beyond the 64-
Kbyte limit of the 16 CPU address lines. The extra addressing capability is provided by a register-based
paging scheme using two additional expansion address lines and the 64 Kbytes of CPU address space.
Six chip-select signals are provided to simplify the interface to external peripheral devices.
Two 8-bit pulse-width modulation timer outputs have been added to the timer system. The two outputs
have selectable polarity, duty cycle, and period. They can be concatenated to form a single 16-bit out-
put.
In addition to the IRQ and XIRQ pins found on other M68HC11 devices, seven more interrupt request
lines have been added, creating a total of one nonmaskable and eight maskable interrupt sources. Re-
fer to the MC68HC11C0 block diagram.
Table 1 Device Ordering Information
Package
64-Pin QFP
Description
No ROM
CONFIG
$00
Frequency
2 MHz
Temperature
–40
°
to + 85
°
C
–40
°
to + 105
°
C
–40
°
to + 125
°
C
3 MHz
68-Pin PLCC
No ROM
$00
2 MHz
0
°
to + 70
°
C
–40
°
to + 85
°
C
–40
°
to + 85
°
C
–40
°
to + 105
°
C
–40
°
to + 125
°
C
3 MHz
0
°
to + 70
°
C
–40
°
to + 85
°
C
MC Order Number
MC68HC11C0CFU2
MC68HC11C0VFU2
MC68HC11C0MFU2
MC68HC11C0FU3
MC68HC11C0CFU3
MC68HC11C0CFN2
MC68HC11C0VFN2
MC68HC11C0MFN2
MC68HC11C0FN3
MC68HC11C0CFN3
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1996
1.1 Features
• M68HC11 CPU
• 256 Bytes of On-Chip Static RAM
• 1024 Bytes of Bootstrap ROM (Available in Single-Chip, Bootstrap, and Special-Test Modes)
• Power Saving STOP and WAIT Modes
• 64 Kbyte Address Space, Expandable to 256 Kbytes Using On-Chip Memory Mapping Logic
• Multiplexed Address/Data Bus
• 16-Bit Timer System
— Three Input Capture (IC) Channels
— Four Output Compare (OC) Channels
— One Additional Channel, Software Selectable as Fourth IC or Fifth OC
• 8-Bit Pulse Accumulator
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog Timer
• Clock Monitor
• Five External General-Purpose Chip Select Signals, Each with Programmable Clock Stretching
• One External Vector/Program Chip Select with Programmable Clock Stretching
• Nine External Interrupt Request Inputs (One Nonmaskable Interrupt)
• Two 8-Bit Pulse-Width Modulation (PWM) Timer Channels (Concatenate for a Single 16-Bit PWM)
• Four-Channel 8-Bit Analog-to-Digital (A/D) Converter
• Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Synchronous Serial Peripheral Interface (SPI)
• Six Input/Output (I/O) Ports (35 Pins)
— 31 Bidirectional
— 4 Input Only
• All Bidirectional Port Pins Have Selectable Internal Pull-Up Devices
• Available in 68-Pin Plastic Leaded Chip Carrier (PLCC) and 64-Pin Quad Flat Pack (QFP)
MOTOROLA
2
MC68HC11C0
MC68HC11C0TS/D
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI
VSS
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
MODB/LIR
PD5/SS/IRQ
PD4/SCK
PD3/MOSI
PD2/MISO/XIRQ
PD1/TxD
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
PG0/CSV/CSPROG
PG1/XA16
PG2/XA17
PG3/GPCS1
PG4/GPCS2
PG5/GPCS3
PG6/GPCS4
PG7/GPCS5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MC68HC11C0
PD0/RxD
PF0/IRQ0
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
VRL
VRH
VSSI
VDDI
Figure 1 Pin Assignments for 64-Pin Quad Flat Pack
MC68HC11C0
MC68HC11C0TS/D
PH0/PW1
PH1/PW2
RESET
AS
E/RD
R/W/WR
EXTAL
XTAL
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MOTOROLA
3
NC
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI
VSS
VDD
9
8
7
6
5
4
3
2
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
MODB/LIR
PD5/SS/IRQ
PD4/SCK
PD3/MOSI
PD2/MISO/XIRQ
PD1/TxD
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
PG0/CSV/CSPROG
PG1/XA16
PG2/XA17
PG3/GPCS1
PG4/GPCS2
PG5/GPCS3
PG6/GPCS4
PG7/GPCS5
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
MC68HC11C0
NC
PD0/RxD
PF0/IRQ0
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
VRL
VRH
VSSI
VDDI
Figure 2 Pin Assignments for 68-Pin PLCC
MOTOROLA
4
PH0/PW1
PH1/PW2
RESET
AS
E/RD
R/W/WR
EXTAL
NC
XTAL
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
MC68HC11C0
MC68HC11C0TS/D
DDRH
PORT H
PWM
XTAL
EXTAL
E/RD
R/W/WR
AS
MODE
CONTROL
PULSE
PAI ACCUMULATOR
PORT A
PORT A DDR
OC2/OC1
OC3/OC1
OC4/OC1
OC5/IC4/OC1
IC1
IC2
IC3
MEMORY
EXPANSION
OSCILLATOR
CLOCK
LOGIC
PH1/PW2
PH0/PW1
MODB/LIR
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
COP
PORT G DDR
PORT G
CHIP
SELECTS
PG7/GPCS5
PG6/GPCS4
PG5/GPCS3
PG4/GPCS2
PG3/GPCS1
PG2/XA17
PG1/XA16
PG0/CSV/CSPROG
TIMER
SYSTEM
VDD
VSS
A/D
CONVERTER
VRH
VRL
PE3/AN3
PE2/AN2
PE1/AN1
PE0/AN0
RESET
PORT F DDR
PORT F
256
BYTES
RAM
INTERRUPT
LOGIC
IRQ[6:0]
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/IRQ0
PORT E
PORT D DDR/DIOCTL
PORT D
PERIODIC
INTERRUPT
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
AN3
AN2
AN1
AN0
HIGH ORDER
ADDRESS
1024
BYTES
BOOT
ROM
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
CPU
LOW ORDER
ADDRESS/DATA
SPI
SS/IRQ
SCK
MOSI
MISO/XIRQ
PD5
PD4
PD3
PD2
SCI
TxD
RxD
PD1
PD0
Figure 3 MC68HC11C0 Block Diagram
MC68HC11C0
MC68HC11C0TS/D
MOTOROLA
5
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