MC74HC4046A
Phase-Locked Loop
High–Performance Silicon–Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase–locked loop contains three phase
comparators, a voltage–controlled oscillator (VCO) and unity gain
op–amp DEMOUT. The comparators have two common signal inputs,
COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self–bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1 OUT and
maintains 90 degrees phase shift at the center frequency between
SIG IN and COMP IN signals (both at 50% duty cycle). Phase
comparator 2 (with leading–edge sensing logic) provides digital error
signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift
between SIG IN and COMP IN signals (duty cycle is immaterial). The
linear VCO produces an output signal VCOOUT whose frequency is
determined by the voltage of input VCO IN signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op–amp output DEMOUT with an external resistor is used where the
VCO IN signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op–amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage–to–frequency conversion and motor speed control.
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MARKING
DIAGRAMS
16
16
1
PDIP–16
N SUFFIX
CASE 648
MC74HC4046AN
AWLYYWW
1
16
16
1
SO–16
D SUFFIX
CASE 751B
1
HC4046A
AWLYWW
16
TSSOP–16
DT SUFFIX
CASE 948F
1
16
SOEIAJ–16
F SUFFIX
CASE 966
1
16
1
HC40
46A
ALYW
16
74HC4046B
AWLYWW
1
•
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Low Power Consumption Characteristic of CMOS Devices
Operating Speeds Similar to LSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0
µA
Maximum (except SIGIN and COMPIN)
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Low Quiescent Current: 80
µA
Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Chip Complexity: 279 FETs or 70 Equivalent Gates
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HC4046AN
MC74HC4046AD
MC74HC4046ADR2
MC74HC4046AF
Package
PDIP–16
SOIC–16
SOIC–16
SOIC–EIAJ
Shipping
2000 / Box
48 / Rail
2500 / Reel
See Note
NO TAG
MC74HC4046AFEL
SOIC–EIAJ
See Note
NO TAG
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 7
Publication Order Number:
MC74HC4046A/D
MC74HC4046A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCOIN
DEMOUT
R1
R2
PC2OUT
SIGIN
PC3OUT
VCC
Name and Function
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) VSS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
PIN ASSIGNMENT
PCPout
PC1out
COMPin
VCOout
INH
C1A
C1B
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
PC3out
SIGin
PC2out
R2
R1
DEMout
VCOin
Î Î
Î Î
Î
Î
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Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
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Î Î
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Î
Î
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ÎÎÎÎ
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Î
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ÎÎÎ
Î Î
Î
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Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Symbol
VCC
Vin
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
±
20
±
25
±
50
750
500
Vout
Iin
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
Iout
DC Output Current, per Pin
ICC
PD
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
Storage Temperature
Plastic DIP†
SOIC Package†
mW
Tstg
TL
– 65 to + 150
260
MAXIMUM RATINGS*
_
C
_
C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP and SOIC Package†
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
ÎÎÎÎ Î
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎ Î
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Symbol
VCC
Parameter
Min
3.0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
VCC
DC Supply Voltage (Referenced to GND) NON–VCO
2.0
0
6.0
V
Vin, Vout
TA
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Pin 5)
VCC
V
– 55
0
0
0
+ 125
1000
500
400
_
C
ns
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
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2
MC74HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH
Parameter
Minimum High–Level Input
Voltage DC Coupled
SIGIN, COMPIN
Maximum Low–Level Input
Voltage DC Coupled
SIGIN, COMPIN
Minimum High–Level
Output Voltage
PCPOUT, PCnOUT
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout|
≤
20
µA
Vout = 0.1 V or VCC – 0.1 V
|Iout|
≤
20
µA
Vin = VIH or VIL
|Iout|
≤
20
µA
Vin = VIH or VIL
|Iout|
≤
4.0 mA
|Iout|
≤
5.2 mA
VCC
Volts
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
– 55 to
25
_
C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
≤
85°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
≤
125°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
(continued)
Unit
V
VIL
V
VOH
V
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS – continued
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL
Parameter
Maximum Low–Level
Output Voltage Qa–Qh
PCPOUT, PCnOUT
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout|
≤
20
µA
Vin = VIH or VIL
|Iout|
≤
4.0 mA
|Iout|
≤
5.2 mA
Iin
Maximum Input Leakage Cur-
rent
SIGIN, COMPIN
Maximum Three–State
Leakage Current
PC2OUT
Maximum Quiescent Supply
Current (per Package)
(VCO disabled)
Pins 3, 5 and 14 at VCC
Pin 9 at GND; Input Leakage
at
Pins 3 and 14 to be excluded
Vin = VCC or GND
VCC
Volts
2.0
4.5
6.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
– 55 to
25
_
C
0.1
0.1
0.1
0.26
0.26
±
3.0
±
7.0
±
18.0
±
30.0
±
0.5
≤
85°C
0.1
0.1
0.1
0.33
0.33
±
4.0
±
9.0
±
23.0
±
38.0
±
5.0
≤
125°C
0.1
0.1
0.1
0.4
0.4
±
5.0
±
11.0
±
27.0
±
45.0
±
10
µA
Unit
V
IOZ
Output in High–Impedance State
Vin = VIH or VIL
Vout = VCC or GND
Vin = VCC or GND
|Iout| = 0
µA
µA
ICC
6.0
4.0
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
tPLH,
tPHL
tPLH,
tPHL
Parameter
Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT
(Figure 1)
Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT
(Figure 1)
VCC
Volts
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
– 55 to 25
_
C
175
35
30
340
68
58
≤
85°C
220
44
37
425
85
72
≤
125°C
265
53
45
510
102
87
Unit
ns
ns
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3
MC74HC4046A
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
tPLH,
tPHL
tPLZ,
tPHZ
tPZH,
tPZL
tTLH,
tTHL
Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT
(Figure 1)
Maximum Propagation Delay, SIGIN/COMPIN Output
Disable Time to PC2OUT (Figures 2 and 3)
Maximum Propagation Delay, SIGIN/COMPIN Output
Enable Time to PC2OUT (Figures 2 and 3)
Maximum Output Transition Time
(Figure 1)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
270
54
46
200
40
34
230
46
39
75
15
13
340
68
58
250
50
43
290
58
49
95
19
16
405
81
69
300
60
51
345
69
59
110
22
19
ns
ns
ns
ns
[VCO Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH
Parameter
Minimum High–Level
Input Voltage
INH
Maximum Low–Level
Input Voltage
INH
Minimum High–Level
Output Voltage
VCOOUT
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout|
≤
20
µA
Vout = 0.1 V or VCC – 0.1 V
|Iout|
≤
20
µA
Vin = VIH or VIL
|Iout|
≤
20
µA
Vin = VIH or VIL
|Iout|
≤
4.0 mA
|Iout|
≤
5.2 mA
VOL
Maximum Low–Level
Output Voltage
VCOOUT
Vout = 0.1 V or VCC – 0.1 V
|Iout|
≤
20
µA
Vin = VIH or VIL
|Iout|
≤
4.0 mA
|Iout|
≤
5.2 mA
Iin
Maximum Input
Leakage Current
INH, VCOIN
Vin = VCC or GND
VCC
Volts
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
6.0
– 55 to
25
_
C
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.1
≤
85°C
2.1
3.15
4.2
0.9
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
1.0
≤
125°C
2.1
3.15
4.2
0.9
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
1.0
µA
V
Unit
V
VIL
V
VOH
V
Min
VVCOIN Operating Voltage Range at
VCOIN over the range
specified for R1; For
linearity see Fig. 15A,
Parallel value of R1 and R2
should be > 2.7 kΩ
R1
Resistor Range
INH = VIL
3.0
4.5
6.0
0.1
0.1
0.1
Max
1.0
2.5
4.0
Min
0.1
0.1
0.1
Max
1.0
2.5
4.0
Min
0.1
0.1
0.1
Max
1.0
2.5
4.0
V
3.0
4.5
6.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
40
40
40
300
300
300
300
300
300
No
Limit
3.0
3.0
3.0
3.0
3.0
3.0
300
300
300
300
300
300
3.0
3.0
3.0
3.0
3.0
3.0
300
300
300
300
300
300
kΩ
R2
C1
Capacitor Range
3.0
4.5
6.0
pF
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4
MC74HC4046A
[VCO Section]
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
Volts
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
3
11
13
See Figures 15A, B, C
– 55 to 25
_
C
Min
Max
≤
85°C
Min
Max
≤
125°C
Min
Max
Unit
%/K
Symbol
∆f/T
Frequency Stability with
Temperature Changes
(Figure 13A, B, C)
VCO Center Frequency
(Duty Factor = 50%)
(Figure 14A, B, C, D)
VCO Frequency Linearity
Parameter
fo
MHz
∆fVCO
%
∂
VCO
Duty Factor at VCOOUT
Typical 50%
%
[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit
VCC
Volts
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
– 55 to 25
_
C
Min
50
50
50
Max
300
300
300
See Figure 12
≤
85°C
Min
Max
≤
125°C
Min
Max
Unit
kΩ
Symbol
RS
Parameter
Resistor Range
Test Conditions
At RS > 300 kΩ the
Leakage Current can
Influence VDEMOUT
Vi = VVCOIN = 1/2 VCC;
Values taken over RS
Range.
VDEMOUT = 1/2 VCC
VOFF
Offset Voltage
VCOIN to VDEMOUT
Dynamic Output
Resistance at DEMOUT
mV
RD
Typical 25
Ω
Ω
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