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MC74VHC1G02
Single 2−Input NOR Gate
The MC74VHC1G02 is an advanced high speed CMOS 2−input
NOR gate fabricated with silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The MC74VHC1G02 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G02 to be used to interface 5 V circuits to 3 V
circuits.
Features
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MARKING
DIAGRAMS
5
SC70−5/SC−88A/SOT−353
DF SUFFIX
CASE 419A
1
1
5
SOT23−5/TSOP−5/SC59−5
DT SUFFIX
CASE 483
1
1
V3
M
G
= Device Code
= Date Code*
= Pb−Free Package
V3 M
G
G
V3M
G
G
M
•
•
•
•
•
•
•
High Speed: t
PD
= 3 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1.0
mA
(Max) at T
A
= 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 56
Pb−Free Packages are Available
IN B
1
5
V
CC
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
IN A
2
1
2
3
PIN ASSIGNMENT
4
OUT Y
IN B
IN A
GND
OUT Y
V
CC
GND
3
Figure 1. Pinout
(Top View)
4
5
FUNCTION TABLE
IN A
IN B
1
Inputs
OUT Y
A
B
L
H
L
H
Y
H
L
L
L
L
L
H
H
Output
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
January, 2007 − Rev. 17
Publication Order Number:
MC74VHC1G02/D
MC74VHC1G02
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
q
JA
T
L
T
J
T
STG
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND
Power Dissipation in Still Air at 85°C
Thermal Resistance
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Storage Temperature Range
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 125°C (Note 5)
SC70−5/SC−88A
TSOP−5
SC70−5/SC−88A (Note 1)
TSOP−5
V
OUT
< GND; V
OUT
> V
CC
V
CC
= 0
High or Low State
Characteristics
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
−0.5 to V
CC
+ 0.5
−20
+20
+25
+50
150
200
350
230
260
)150
*65
to
)150
> 2000
> 200
N/A
$500
Unit
V
V
V
mA
mA
mA
mA
mW
°C/W
°C
°C
°C
V
I
LATCHUP
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 3.3 V
$
0.3 V
V
CC
= 5.0 V
$
0.5 V
Characteristics
Min
2.0
0.0
0.0
−55
0
0
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
T
J
= 130°C
T
J
= 120°C
T
J
= 100°C
T
J
= 110°C
T
J
= 90°C
T
J
= 80°C
100
TIME, YEARS
1
1
10
1000
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G02
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Test Conditions
V
CC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
V
IN
= V
IH
or V
IL
I
OH
= −50
mA
V
IN
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 to
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
$0.1
1.0
2.0
3.0
4.5
T
A
= 25°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
$1.0
10
Typ
Max
T
A
≤
85°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.34
3.66
0.1
0.1
0.1
0.52
0.52
$1.0
40
mA
mA
V
Max
−55
≤
T
A
≤
125°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
Max
Unit
V
V
IL
Maximum Low−Level
Input Voltage
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
V
V
Î
Î
Î
ÎÎ Î Î Î Î ÎÎ
Î Î Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î ÎÎ Î
Î
Î
Î ÎÎ Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î ÎÎ Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎ Î Î
Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î
Î
Î
Î Î Î Î Î ÎÎ Î
Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î Î Î ÎÎ Î
Î Î Î Î Î ÎÎ Î
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎ Î
Î Î Î ÎÎ Î
Î ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
Input t
r
= t
f
= 3.0 ns
Symbol
t
PLH
,
t
PHL
Parameter
Test Conditions
T
A
= 25°C
Typ
4.0
5.4
3.0
3.8
5.5
T
A
≤
85°C
−55
≤
T
A
≤
125°C
Min
Max
11.0
15.5
Min
Max
7.9
11.4
5.5
7.5
10
Min
Max
Unit
ns
Maximum Propagation
Delay,
Input A or B to Y
V
CC
= 3.3
$
0.3 V
V
CC
= 5.0
$
0.5 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
9.5
13.0
6.5
8.5
10
8.0
10.0
10
C
IN
Maximum Input
Capacitance
pF
Typical @ 25°C, V
CC
= 5.0 V
11
C
PD
Power Dissipation Capacitance (Note 6)
pF
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
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3
MC74VHC1G02
TEST POINT
A or B
50%
GND
t
PLH
Y
t
PHL
C
L
*
V
CC
INPUT
OUTPUT
50% V
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
Figure 5. Test Circuit
ORDERING INFORMATION
Device
MC74VHC1G02DFT1
MC74VHC1G02DFT1G
MC74VHC1G02DFT2
MC74VHC1G02DFT2G
MC74VHC1G02DTT1
MC74VHC1G02DTT1G
Package
SC70−5/SC−88A/SOT−353
SC70−5/SC−88A/SOT−353
(Pb−Free)
SC70−5/SC−88A/SOT−353
SC70−5/SC−88A/SOT−353
(Pb−Free)
SOT23−5/TSOP−5/SC59−5
SOT23−5/TSOP−5/SC59−5
(Pb−Free)
3000/Tape & Reel
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
stm32/stm8
