MC80364K64
M
O
S
YS
Low Power 3.3V/2.5V
64Kx64 PBSRAM
®
•
High performance, low power pipeline burst SRAM
Ultra low power single chip 512Kbyte Cache
for green PC and battery powered PC
VSSQ - 39
N/C - 40
MODE - 41
A15 - 42
A14 - 43
A13 - 44
VDD - 45
VSS - 46
A12 - 47
A11 - 48
A10 - 49
A9 - 50
A8 - 51
N/C - 52
A7 - 53
A6 - 54
A5 - 55
A4 - 56
A3 - 57
VDD- 58
VSS - 59
A2 - 60
A1 - 61
A0 - 62
ZZ - 63
VDDQ- 64
•
High performance
83-133MHz Speed grades
3-1-1-1 Burst Read
1-1-1-1 Burst Write
3-1-1-1-1-1-1-1... pipeline operation
•
Low power
Low active power
Ultra low power ZZ standby mode
Single 3.3V supply (V
DD
)
Isolated 3.3V or 2.5V I/O supply (V
DDQ
)
•
Compatibility
Individual Byte Write and Global Write masking
Interleave and burst address support
Three chip enables for easy expansion
Industry standard 128-Pin PBSRAM pinout
Industry standard PBSRAM specification
•
Applications
®
™
Pentium and PowerPC pipelined L2 Cache
Ideal for high speed, low power communica-
tions buffers
Power sensitive portable and DSP applications
VSSQ - 65
DQ0 - 66
DQ1 - 67
DQ2 - 68
DQ3 - 69
DQ4 - 70
DQ5 - 71
DQ6 - 72
DQ7 - 73
DQ8 - 74
DQ9 - 75
DQ10 - 76
VDDQ - 77
VSSQ - 78
DQ11 - 79
DQ12 - 80
DQ13 - 81
DQ14 - 82
DQ15 - 83
DQ16 - 84
DQ17 - 85
DQ18 - 86
DQ19 - 87
DQ20 - 88
VDDQ - 89
VSSQ - 90
DQ21 - 91
DQ22 - 92
DQ23 - 93
DQ24 - 94
DQ25 - 95
DQ26 - 96
DQ27 - 97
DQ28 - 98
DQ29 - 99
DQ30 - 100
DQ31 - 101
VDDQ - 102
128 Lead Plastic Quad Flat Pack
LQFP -- 14 mm x 20 mm x 1.4 mm
38 - VDDQ
37 - DQ63
36 - DQ62
35 - DQ61
34 - DQ60
33 - DQ59
32 - DQ58
31 - DQ57
30 - DQ56
29 - DQ55
28 - DQ54
27 - DQ53
26 - VSSQ
25 - VDDQ
24 - DQ52
23 - DQ51
22 - DQ50
21 - DQ49
20 - DQ48
19 - DQ47
18 - DQ46
17 - DQ45
16 - DQ44
15 - DQ43
14 - VSSQ
13 - VDDQ
12 - DQ42
11 - DQ41
10 - DQ40
9 - DQ39
8 - DQ38
7 - DQ37
6 - DQ36
5 - DQ35
4 - DQ34
3 - DQ33
2 - DQ32
1 - VSSQ
128 - VDDQ
127 - CE3
126 - CE2
125 - CE3#
124 - CE2#
123 - VSS
122 - VDD
121 - CE#
120 - BW8#
119 - BW7#
118 - BW6#
117 - BW5#
116 - OE#
115 - CLK
114 - BWE#
113 - GW#
112 - BW4#
111 - BW3#
110 - VSS
109 - VDD
108 - BW2#
107 - BW1#
106 - ADSC#
105 - ADSP#
104 - ADV#
103 - VSSQ
Figure 1. Pin Function
______________________________________________
Overview
The MoSys MC80364K64 is a high performance,
low power pipeline-burst-SRAM (PBSRAM). Fabri-
cated using an advanced low power, high perform-
ance CMOS process, the MoSys MC80364K64 is
pin and function compatible with industry standard
32Kx64 PBSRAM specification.
The MoSys MC80364K64 supports PBSRAM oper-
ating modes at maximum burst frequency including
indefinite pipeline read or write (3-1-1-1-1-1-1...)
Available in 64Kx64 capacity, the MoSys
MC80364K64 is packaged in a standard 128 lead
LQFP.
Sleep Mode
MoSys x64 Pipeline Burst Cache supports sleep
mode (ZZ).
Low Power
The MC80364K64 affords systems dramatic power
savings due to the benefits of it’s proprietary Mo-
Sys technology. Peak operating power of typical
PBSRAM is 7x that of MC8036K64. Making it ideal
for portable applications, as well as applications
requiring a large amount of RAM.
Part Number Designation
Example:
MC80364K64L-10
Device Designation:
MC8,
Series:
03
Organization:
64K64
Package Type: L=LQFP
Speed:
–10
= 100 MHz
DS10 Rev 1.4 – 12/29/98
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Page 1
MC80364K64
M
O
S
YS
Low Power 3.3V/2.5V
64Kx64 PBSRAM
®
Table 1. Pin Description
Pin Number
62, 61, 60, 57, 56, 55, 54, 53, 51, 50,
49, 48, 47, 44, 43, 42
107, 108, 111, 112, 117, 118, 119, 120
113
114
115
121
124
125
126
127
116
104
105
106
63
66, 67,68, 69, 70, 71, 72, 73, 74, 75, 76,
79, 80, 81, 82, 83, 84, 85, 86 ,87, 88,
91,92, 93, 94, 95, 96, 97, 98, 99, 100,
101, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15,
16, 17, 18, 19, 20, 21, 22 ,23, 24, 27,
28, 29, 30, 31, 32, 33, 34, 35, 36, 37
41
40, 52
122, 109,58, 45
123, 110, 59, 46
13, 25, 38, 64, 77, 89, 102 128
1, 14, 26, 39, 65, 78, 90, 103,
Table 2. Absolute Maximum Ratings
Symbol
Parameter
VDD
VDDQ
Vih
Vil
Ts
Core Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
VSSQ-0.5
-65
150
Symbol
A[15:0]
BW[8:1]#
GW#
BWE#
CLK
CE#
CE2#
CE3#
CE2
CE3
OE#
ADV#
ADSP#
ADSC#
ZZ
DQ[63:0]
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Description
Processor Addresses
Processor host bus byte enables.
Global Write from cache controller
Byte Write Enable from controller
Processor host bus clock
ADSP# mask and ADSC# chip enable
Depth expansion chip enable
Depth expansion chip enable
Depth expansion chip enable
Depth expansion chip enable
Asynchronous output enable
Burst address counter advance
ADS# of processor
ADS# of controller
Sleep-mode: ZZ
Data I/O pins
MODE
N/C
VDD
VSS
VDDQ
VSSQ
Input
-
3.3 Volts
Ground
I/O Supply
I/O Ground
Burst Mode Select
Not connected internally
Power
Ground
I/O Buffer Supply
I/O Buffer Ground
Min
Max
3.6
3.6
VDDQ +0.5
Units
V
V
V
V
°C
Notes:
Max Vih is not to exceed maximum VDDQ
DS10 Rev 1.4 – 12/29/98
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Page 2
MC80364K64
M
O
S
YS
Low Power 3.3V/2.5V
64Kx64 PBSRAM
®
Table 3. Recommended Operating Conditions
Symbol
Parameter
VDD
VDDQ
Vih
Vil
Voh1
Voh2
Vol
Topr
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Temperature
Condition
3.3V +10%/-5%
2.5V +44%/-5%
Min
3.135
2.375
1.7
-0.3
Max
3.6
3.6
VDDQ + .3
0.8
Units
V
V
V
V
V
V
Ioh = -5 mA
VDDQ = 3.3V
Ioh = -5 mA
VDDQ = 2.5V
Iol = 5 mA
2.4
2.0
0.4
0
70
V
°C
Table 4. Absolute Maximum AC Operating Conditions
Symbol
Parameter
Vih
Vil
tOVR
tSET
Input High Voltage
Input Low Voltage
Overshoot/Undershoot Voltage Duration
Overshoot/Undershoot Settling Time
Min
1.7
VSSQ - 1.0
Max
VDDQ+1.0
0.8
0.2*tCY
0.8*tCY
Unit
s
V
V
ns
ns
Table 5. Maximum DC Current Requirements
Symbol
Condition
I
DD
I
DD1
Operating current, device selected; all inputs < Vil or >
Vih; cycle time > tKC min, VCC = max, 0 pF load
Idle current, device selected; ADSP#, ADSC#, GW#,
BW#s, ADV# and all other inputs > 2.8 volts; cycle time >
tKC min, VCC = max, 0 pF load
Clock stopped, all inputs > 2.8 v, VCC = max
Sleep mode, clock stopped, all inputs > 2.8 v, VCC = max
2.5V
Supply
10
2
3.3V
Supply
50
15
Units
mA
mA
I
DD2
I
DDZZ
1
1
1
1
mA
mA
Table 6. Maximum DC Current Requirements
Symbol
C
I
C
I/O
Input Pin Capacitance
I/O Pin Capacitance
Parameter
Max
4
6
Units
pF
pF
DS10 Rev 1.4 – 12/29/98
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Page 3
MC80364K64
M
O
S
YS
Low Power 3.3V/2.5V
64Kx64 PBSRAM
®
Table 7. AC Timing Characteristics at Recommended Operating Conditions
-7R5
(133 MHz)
Sym
tAAH
tAAS
tADSH
tADSS
tAH
tAS
tCEH
tCES
tDH
tDS
tKC
tKH
tKL
tKQ
tKQHZ
tKQLZ
tKQX
tOELZ
tOEHZ
tOEQ
tOEQX
tWS
tWH
tZZs
tZZREC
Parameter
ADV# hold
ADV# setup
ADSx# hold
ADSx# setup
Address hold
Address setup
Chip Enable hold
Chip Enable setup
Write Data hold
Write Data setup
Clock cycle
Clock high
Clock low
Clock to output valid
Clock to output high-Z
Clock to output low-Z
Clock to output invalid
OE# to output low-Z
OE# to output high-Z
OE# to output valid
OE# to output invalid
GW#, BWx# setup
GW#, BWx# hold
ZZ standby
ZZ recovery
100
0
2
0.5
100
100
1.5
0
1.5
0
4.5
4.5
0
2
0.5
100
100
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
7.5
2
2
4.5
7.5
1.5
0
1.5
0
4.8
4.8
0
2
0.5
100
100
Max
-8R5
(117 MHz)
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
8.5
2.5
2.5
4.75
8.6
1.5
0
1.5
0
5.5
5.5
0
2
0.5
100
Max
-10
(100 MHz)
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
10
3.2
3.2
5
10
1.5
0
1.5
0
6
6
Max
-12
(83 MHz)
Min
0.5
2
0.5
2
0.5
2
0.5
2
0.5
2
12
4
4
6
12
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: VDDQ = 2.5V (+44%/-5%), VDD = 3.3V (+10%/-5%)
DS10 Rev 1.4 – 12/29/98
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Page 4
MC80364K64
M
O
S
YS
Low Power 3.3V/2.5V
64Kx64 PBSRAM
®
Single Read
tKC
Burst Read
Pilpeline Read
Unselected
CLK
tADSS
tADSH
tKH tKL
ADSP# is blocked by CE1# inactive
ADSP#
tADSS
tADSH
ADSC# initiated read
ADSC#
Suspend Burst
ADV#
tAS
tAH
A[15:0]
GW#
RD1
tWS
RD2
tWH
RD3
tWS
tWH
BWE#
BW[4:1]
tCES
tCEH
CE1# masks ADSP#
CE#
tCES
tCEH
CE2 and CE3# only sampled with ADSP# and ADSC#
Unselected with CE2
CE2
tCES
tCEH
CE3#
tOEQ
tOEHZ
OE#
tOELZ
tOEQX
tKQX
tKQX
Data-Out
Data-In
tKQLZ
tKQ
1a
2a
2b
2c
2d
3d
tKQHZ
Figure 2 Read Cycle Timing
DS10 Rev 1.4 – 12/29/98
© 1998 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
Page 5
