MC9S12DT128
Device User Guide
Covers MC9S12DT128E, MC9S12DG128E,
MC9S12DJ128E, MC9S12DG128, MC9S12DJ128,
MC9S12DB128, MC9S12A128, SC515846, SC515847,
SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204,
SC102205
HCS12
Microcontrollers
9S12DT128DGV2/D
V02.17
03 Jun 2010
freescale.com
Device User Guide — 9S12DT128DGV2/D V02.17
Revision History
Version Revision Effective
Number
Date
Date
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
18 Jun
2001
23 July
2001
23 Sep
2001
12 Oct
2001
27 Feb
2002
4 Mar
2002
18 June
2001
23 July
2001
23 Sep
2001
12 Oct
2001
27 Feb
2002
4 Mar
2002
Author
Description of Changes
Initial version (parent doc v2.03 dug for dp256).
Updated version after review
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
Replaced Star12 by HCS12
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
NEW MASKSET
Changed part number from DTB128 to DT128
Functional Changes:
ROMCTL changes in Emulation Mode
80 Pin Byteflight package Option available
Flash with 2 Bit Backdoor Key Enable
Additional CAN0 routing to PJ7,6
Improved BDM with sync and acknowledge capabilities
New Part ID number
Improvements:
Significantly improved NVM reliability data
Corrections:
Interrupt vector Table
Updated Block User Guide versions in preface
Updated Appendix A Electrical Characteristics
V01.06
8 July
2002
22 July
2002
V02.00
11 Jan
2002
11 Jan
2002
V02.01
01 Feb
2002
01 Feb
2002
2
Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17
Version Revision Effective
Number
Date
Date
Author
Description of Changes
Changed XCLKS to PE7 in Table 2-2
Updated device part numbers in Figure 2-1
Updated BDM clock in Figure 3-1
Removed SIM description in overview & n
UPOSC
spec in Table A-15
Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH
(Table A-6), C
INS
(Table A-9), C
IN
(Table A-6 & A-15),
Updated interrupt pulse timing variables in Table A-6
Updated device part numbers in Figure 2-1
Added document numbers on cover page and Table 0-2
Cleaned up Fig. 1-1, 2-1
Updated Section 1.5 descriptions
Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.
Corrected NVM sizes in Sections 16, 17
Added I
REF
spec for 1ATD in Table A-8
Added Blank Check in A.3.1.5 and Table A-11
Updated CRG spec in Table A-15
Added:
Pull-up columns to signal table,
Example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Device specific info on CRG
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
Changed leakage current for ADC inputs down to +-1uA
Minor modification of PLL frequency/ voltage gain values
Corrected:
Pin names/functions on 80 pin packages
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
Corrected:
Register address mismatches in 1.5.1
Removed document order no. from Revision History pages
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing
CAN0/1/4, BDLC, IIC and/or Byteflight
Added 2L40K mask set in section 1.6
Added OSC User Guide in Preface, “Document References”
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Added new section: “Oscillator (OSC) Block Description”
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
V02.02
08 Mar
2002
08 Mar
2002
V02.03
14 Mar
2002
14 Mar
2002
V02.04
16 Aug
2002
16 Aug
2002
V02.05
12 Sep
2002
12 Sep
2002
V02.06
06 Nov
2002
06 Nov
2002
Freescale Semiconductor
3
Device User Guide — 9S12DT128DGV2/D V02.17
Version Revision Effective
Number
Date
Date
Author
Description of Changes
Added 3L40K mask set in section 1.6
Corrected register entries in section 1.5.1 “Detailed Memory Map”
Updated description for ROMCTL in section 2.3.31
Updated section 4.3.3 “Unsecuring the Microcontroller”
Corrected and updated device-specific information for OSC
(section 8.1) & Byteflight (section 15.1)
Updated footnote in Table A-4 “Operating Conditions”
Changed reference of VDDM to VDDR in section A.1.8
Removed footnote on input leakage current in Table A-6 “5V I/O
Characteristics”
Added part numbers MC9S12DT128E, MC9S12DG128E, and
MC9S12DJ128E in “Preface” and related part number references
Removed mask sets 0L40K and 2L40K from Table 1-3
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;
updated Fig.3-1 “Clock Connections” to show the individual HCS12
blocks
Corrected PIM module name and document order number in Table
0-2 “Document References”
Corrected ECT pulse accumulators description in section 1.2
“Features”
Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments
Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in
Table 2.1 “Signal Properties”
Mentioned “S12LRAE” bootloader in Flash section 17
Corrected footnote on clamp of TEST pin under Table A-1
“Absolute Maximum Ratings”
Corrected minimum bus frequency to 0.25MHz in Table A-4
“Operating Conditions”
Replaced “burst programming” by “row programming” in A.3 “NVM,
Flash and EEPROM”
Corrected blank check time for EEPROM in Table A-11 “NVM
Timing Characteristics”
Corrected operating frequency in Table A-18 “SPI Master/Slave
Mode Timing Characteristics
Added A128 information in “Derivative Differences”, 2.1 “Device
Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4
Added lead-free package option (PVE) in Table 0-2 “Derivative
Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber
Example”
Added an “AEC qualified” row in the “Derivative Differences” tables
0-1 & 0-2.
Added part numbers SC515846, SC515847, SC515848, and
SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,
and section 23.
Corrected and added maskset 4L40K in tables 0-1 & 0-2 and
section 1.6.
Corrected BDLC module availability in DB128 80QFP part in
“Derivative Differences” table 0-2.
V02.07
29 Jan
2003
29 Jan
2003
V02.08
26 Feb
2003
26 Feb
2003
V02.09
15 Oct
2003
15 Oct
2003
V02.10
6 Feb
2004
6 Feb
2004
V02.11
3 May
2004
3 May
2004
4
Freescale Semiconductor
Device User Guide — 9S12DT128DGV2/D V02.17
Version Revision Effective
Number
Date
Date
06 Dec
2004
06 Dec
2004
Author
Description of Changes
Added maskset 0L94R
Added items V
IH,EXTAL
, V
IL,EXTAL
, & V
HYS,EXTAL
in table A-15
“Oscillator characteristics”
Removed item “Oscillator” from table A-4 “Operating Conditions” as
it is already covered in table “Oscillator Characteristics”
Amended feature list of A128 in Table 0-1 “Derivative Differences”
Updated cover page
Added part numbers SC101161DT, SC101161DG, SC101161DJ,
SC102202, SC102203, SC102204, & SC102205
Added masksets 5L40K &1L59W
Changed T
Javg
to 85°C in table A-12 “NVM Reliability” & added
footnote concerning data retention
Updated “NVM Reliability” table A-12 format with added data.
Added figure A-2 “Typical Endurance vs Temperature”
Added maskset 2L94R
Added maskset 1L59W for MC9S12A128
V02.12
V02.13
04 Mar
2005
04 Mar
2005
V02.14
28 Apr
2005
28 Apr
2005
V02.15
V02.16
V02.17
05 Oct
2005
12 Apr
2008
3 Jun
2010
05 Oct
2005
12 Apr
2008
3 Jun
2010
Freescale Semiconductor
5
