MC9S12UF32
System on a Chip Guide
V01.05
Original Release Date: 17 JAN 2002
Revised: 03 Dec 2004
TSPG - 8/16 Bit MCU Design, HKG
Freescale Semiconductor, Inc.
This product has been designed for use in “Commercial” applications. Please see a description below.
Freescale’s semiconductor products are classified into the following three tiers “Commercial”, “Industrial”, and “Automotive”. A
product should only be used in applications appropriate to its tier. The recommended applications for products in the different
tiers are indicated below. For questions, please contact a Freescale sales representative.
Commercial: Typically 5 year applications - personal computers, PDA’s, portable telecom products, consumer electronics, etc.
Industrial: Typically 10 year applications - installed telecom equipment, work stations, servers, etc. These products can also
be used for Commercial applications.
Automotive: Qualified per automotive industry standard methods.
Revision History
Release
Number
00.01
00.02
00.03
Date
17JAN02
19FEB02
26APR02
Author
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Initial Version
Summary of Changes
Modified SMRAM mapping to allow 1k byte 16-bit block mappable
to Vector Space. Update spec with review feedback.
Modified Device pinout to separate D+ D- for high speed and low
speed operation. Remap Timer pins to Port R. Update BG
references.
Modified Device pinout per IP requirement
Add SCI
Update Interrupt information.
Change pin location for REF3V and VREGEN
minor update on module name references
remove references to pseudo stop and clock monitor
- Updated info for SMRAM3P5K2E in device memory map
- Updated EXTAL and XTAL supply rail information.
- Relocate SCI module base address from $70 to $C8
- Relocate ATA5HC module base address from $240 to $1C0
- Relocate PIM module base address from $80 to $240
- Relocate Interrupt Vectors
- Updated Phy evaluation pinout.
- Updated CFA00, CFA01 and CFA02 pin name to CFA0, CFA1 and
CFA2 respectively.
- Removed ESD and Latchup section in Electrical.
- Update Block Guide References
- Miscellaneous Typo mistakes.
- Update typo in interrupt vector table for Vector $C2
- Update typo in pin order of IOC[7:4] in signal properties table
- Specify run and wait IDDs in Electrical Section
- Specify stop IDD at room temperature in Electrical Section
- Change specification to include 64 pin option
- ROMCTL pin assigned to PJ2
00.04
16SEP02
Y.H. Cheng
00.05
25SEP02
Y.H. Cheng
00.06
03JUN03
Y.H. Cheng
00.07
11JUN03
Y.H. Cheng
00.08
13JUL03
Y.H. Cheng
Freescale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability,
function or design. Freescale Semiconductor does not assume any liability arising out of the application or use of any product or
circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Freescale
Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or
use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part. Freescale
TM
and the Freescale logo are registered trademarks of Freescale
Semiconductor, Inc. Freescale Semiconductor, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Freescale Semiconductor, Inc. 2004
Freescale Semiconductor
2
System on a Chip Guide — 9S12UF32DGV1/D V01.05
Release
Number
Date
Author
Summary of Changes
- Removed all references to XCLKS, since function is removed.
- typo - replaced PRU with RPU.
- typo - replaced ATAHC with ATA5HC
- Removed references to clock monitor, since function is not
available.
- Update
θ
JA
for 100-pin and 64-pin packages.
- Add footnotes on IRQ pin removal in 64-pin package
- Update Flash memory map out of reset.
- Add information on INITRM, INITRG, INITEE setting for example
application memory map
- Update clock distribution diagram to make it more intelligible
- Change table 2-3, 2-5 description using general purpose port
references instead of Functional module references.
- Stop IDD spec for -40C and 85C are removed
- Add other conditions for RUN Idd and Wait Idd.
- Minor typo corrections.
- Corrected ‘Background Debug Module’ to ‘HCS12 Breakpoint’ at
address $0028-$002F in table 1-1.
- Added detailed register map.
- Corrected the MSHC enable control in table 5-1.
- Added part ID $6311 for mask 1L47S.
- Removed all references and description on USB Physical
Endpoint 6
- Updated IDD, 3V and 5V I/O electricals and package thermal
resistance information
- Include Commercial tier note
- Update and add note to detailed register map.
- Added PIM reference.
- Added package information as appendix B.
- Improved fig 1-1.
- Fixed consistency of 3.0v and 3.3v for VDD3X.
- Updated power dissipation formula.
- Added schematic and PCB layout recommendations.
- Added NVM, VREGU, CRGU electricals to appendix A.
01.00
21AUG03
Y.H. Cheng
01.01
28NOV03
Wai-On Law
01.02
23MAR04
Y.H. Cheng
01.03
01.04
20APR04
10MAY04
Wai-On Law
Wai-On Law
01.05
03DEC04
Wai-On Law
Freescale Semiconductor
3
System on a Chip Guide — 9S12UF32DGV1/D V01.05
4
Freescale Semiconductor
System on a Chip Guide — 9S12UF32DGV1/D V01.05
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.2
Signal Properties Summary for 100-pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.3
Signal Properties Summary for 64-pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.4
Detailed Signal Descriptions for 100-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.1
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.2
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.3
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.4
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.5
BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin . . . . . . . . . .57
2.4.6
RPU — USB D+ pull up resistor termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.7
RREF — External bias resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.4.8
DPF - USB Full Speed D+ data line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.9
DPH - USB High Speed D+ data line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.10 DMF - USB Full Speed D- data line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.11 DMH - USB High Speed D- data line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.12 PWROFF5V - power off 5V supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.13 PWROFF3V - power off 3V supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.14 REF3V - 3.3V reference for external regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.4.15 PA[7:0] / ADDR[15:8] / DATA[15:8] / CFD[15:8] / ATAD[15:8] — Port A I/O Pins . . .58
2.4.16 PB[7:0] / ADDR[7:0] / DATA[7:0] / CFD[7:0] / ATAD[7:0] — Port B I/O Pins . . . . . . .59
2.4.17 PE7 / NOACC — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.4.18 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.4.19 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
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