MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM20114/D
ImageMOS
Preliminary Advance Information
640 x 480 pixel
Color VGA Digital Image Sensor
progressive scan solid state image sensor with
integrated CDS/PGA/ADC, digital programming,
control, timing, and pixel correction features
Features:
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VGA resolution, active CMOS image sensor with square
pixel unit cells
5.6µm pitch pixels with patented pinned photodiode
architecture
RGB color filter array with micro lenses
High sensitivity, quantum efficiency, and charge
conversion efficiency
Low fixed pattern noise / wide dynamic range
Global and continuous variable speed shutter
Single master clock operation- 15MHz Max
Digitally programmable via I
2
C interface
Integrated on-chip timing/logic circuitry
Single 3.3V power supply with optional 2.7V Digital I/O
support
Low Power consumption - 100mW @ 30 fps
CDS sample and hold for suppression of low frequency
and correlated reset noise
1-9x programmable variable gain to optimize dynamic
range and facilitate white balance and iris adjustment
10-bit, pipelined algorithmic RSD ADC (DNL +0.5 LSB, INL
+1.0 LSB)
Pixel addressability to support ‘Window of Interest’
windowing, resolution, and subsampling
Digitally controlled encoded data stream
30 fps full VGA at 13.5 MHz Master Clock Rate
36 pin CLCC package
MCM20114
VGA CMOS Sensor
Part Number
MCM20114IBBL
Description
Color RGB sensor
with Lenslets
Monochrome
sensor without
Lenslets
Package
36 Pin CLCC
MCM20114IBMN
36 Pin CLCC
SIDEWINDER
Integrated VGA Image Module -
complete w/ a MCM20114 and 1/4”
Optic.
The MCM20114 is a fully integrated, high performance CMOS image sensor with features such as integrated timing,
control, and analog signal processing for digital imaging applications. The part provides designers a complete im-
aging solution with a monolithic image capture and processing engine thus making it a true “camera on a chip”. Sys-
tem benefits enable design of smaller, portable, low cost and low power systems. Thereby making the product
suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automo-
tive among others.
The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using Motorola’s
sub-micron ImageMOS
TM
technology. A maximum frame rate of 30 FPS at full resolution can be achieved, further
the frame rate is completely adjustable, independent of the system clock. Each pixel on the sensor is individually
addressable allowing the user to control “Window of Interest” (WOI) panning and zooming. Control of sub-sam-
pling, resolution, exposure, gain, and other image processing features is accomplished via a two pin I
2
C interface.
The sensor is run by supplying a single Master Clock. The sensor output is 10 digital bits providing wide dynamic
range images.
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
©
MOTOROLA, INC. 2001
Revision 1.0 - June 12, 2001 :
MCM20114
1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Specifications
Image Size:
3.584 mm x 2.688 mm (4.48 mm Diagonal, 1/4” Optic)
Resolution:
668 x 488 pixels, available digital zoom and region of interest (ROI) windowing
Pixel Size:
5.6µm x 5.6µm
Monochrome Sensitivity:
1.68 V/Lux-sec
Min. Detectable Light Level:
5 Lux @ 30Fps with F/1.8 lens
Shutter Modes:
Global shutter, continuous or single frame rolling shutter modes available
Readout Rate:
15.0 MSPS
Frame Rate:
0-30 Full frames (640x480) per second
Master Clock Frequency:
2.0 - 15.0MHz
System Dynamic Range:
60dB
On Chip programmable gain:
0dB to 19.1dB
On Chip Image Correction:
Programmable offset non-uniformity correction
Analog to Digital Converter:
10-bit, RSD ADC (DNL +/-0.5 LSB, INL +/-1.0 LSB)
Power Dissipation:
100mW RMS, operating @13.5Mhz
Package:
36 pin ceramic LCC
Temperature Operating Range:
-10 to 40
o
C
MCLK
INIT
652 x 490 pixels
(656 x 502 total including
dark and isolation)
Digital
Control
Sensor
Interface
I2C Serial
Interface
SYNC
SCLK
SDATA
CDS
Post ADC
Column
Offset
White
Balance
Global
Gain
Global
Offset
ADC(9:0)
HCLK
FRC
10 Bit
ADC
Control Signal
Encoding
VCLK
SOF
Figure 1. MCM20114 Simplified Block Diagram
MOTOROLA
Revision 1.0 - June 12, 2001 :
MCM20114
2
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
656
6Dark + 6Isolation
SOF
2Dark +2Isolation
VCLK
HCLK
Master Row Sequencer, Integration
Control, and Timing generator
Roe Decoder and Drivers
2Dark +2Isolation
490
Image Sensor Pixel Array
502
652
2
1
1 2
6Dark +6Isolation
Column
Sequencer
& Drivers
Column Decode, Sensing, and Muxing
INIT
SYNC
Color
Sequencer
Analog
Switch
6
6
6
6
I
2
C Serial
Interface
SDATA
SCLK
MCLK
AIN
Column
Offset
Calibration
6
6
6
6
I
2
C Register
Decode
ADC9
Frame
Rate
Clamp
Column
DOVA
WB
PGA
1.0x - 3.0x
Global
PGA
1.0x - 3..0x
1.5x
Global
Dova
2.0x
10 Bit
RSD
Pipelined
ADC
ADC8
ADC7
ADC6
10
ADC5
ADC4
CLRCA
CLRCB
CVREFM
CVREFP
IBIAS
IBIASADC
Post ADC
Processing
Bandgap
Reference
and Bias
Generation
ADC3
Test
Monitor
Logic
10
ADC2
ADC1
ADC0
V
refp
V
refm
V
cm
I
bias
Analog Circuits
Digital Logic
CVAG
CVCMADC
CVAGREF
CVBG
Figure 2. MCM20114 Detailed Block Diagram
Revision 1.0 - June 12, 2001 :
MCM20114
MOTOROLA
3
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Pin Definitions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
DVDDC
MCLK
DVSS
PIX_OUT0
PIX_OUT1
PIX_OUT4
PIX_OUT5
HCLK
VCLK
SOF
SCLK
SDATA
AVDD
AVSS
AIN
CLRCA
CLRCB
CVAGREF
CVAG
CVBG
CVREFM
Function
Digital Core Power
Master Clock
Digital I/O and Core Return
Data Output 0 (LSB)
Data Output 1
Data Output 4
Data Output 5
Horizontal output clock
Vertical output clock
Start of Frame, readout data
begin signal
I
2
C Clock
I
2
C Data
Analog Power
Analog Power Return
Analog Input Signal/Reset
Test
Frame Rate Clamp
Reference A
Frame Rate Clamp
Reference B
Common Mode Reference
Common Mode Reference
Bandgap Voltage Reference
ADC Reference Bottom
I/O
P
I
P
O
O
O
O
O
O
O
I
I/O
P
P
I
I
I
I
I
I
I
Pixel Data Valid Signal
(Default Active High)
Line Sync signal
(Default Active High)
Indicates begining of Frame data read-
out (Active High)
Pull-up resistor required
Pull-up resistor required
(3.3V +/-10%)
Ground
During Normal operation - Set to
Ground
During Normal operation - Bypass w/
0.1uF Capacitor
During Normal operation - Bypass w/
0.1uF Capacitor
During Normal operation - Bypass w/
0.1uF Capacitor
During Normal operation - Bypass w/
0.1uF Capacitor
During Normal operation - Bypass w/
0.1uF Capacitor
During Normal operation - Bypass w/
0.1uF Capacitor
Description
(3.3V +/-10%)
15 MHz Maximum Frequency -
0-DVDDIO Volts @ 50% Duty Cycle.
Ground
MOTOROLA
Revision 1.0 - June 12, 2001 :
MCM20114
4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Pin
22
23
24
25
26
27
28
Name
CVREFP
CVCMADC
IBIAS
AVSS
AVDD
IBIASADC
SYNC
Function
ADC Reference Top
ADC Common Mode
Reference
Analog Bias Input
Analog Power Return
Analog Power
ADC Bias Input
Start Data Capture
I/O
I
I
I
Description
During Normal operation - Bypass w/
0.1uF Capacitor
During Normal operation - Bypass w/
0.1uF Capacitor
Optional external resistor - Tie to nn KΩ
resistor
Ground
(3.3V +/-10%)
Optional external resistor - Tie to nn KΩ
resistor
Initiates a single frame capture in Global
Shutter and SFRS modes
(Default Active High)
ACTIVE HIGH - Synchronous Reset, 4
MCLKs signal wide
P
P
I
I
29
30
31
32
33
34
35
36
INIT
Initialize Signal - Sensor
Reset
Data Output 9 (MSB)
Data Output 8
Data Output 7
Data Output 6
Data Output 3
Data Output 2
Digital I/O Power
I
O
O
O
O
O
O
P
PIX_OUT9
PIX_OUT8
PIX_OUT7
PIX_OUT6
PIX_OUT3
PIX_OUT2
DVDDIO
(3.3V +10% to 2.7V -5%)
©
MOTOROLA, INC. 2001
Revision 1.0 - June 12, 2001 :
MCM20114
5
