MOTOROLA
Order this document
by MCM36800/D
SEMICONDUCTOR
TECHNICAL DATA
MCM36800
8M x 36 Bit Dynamic Random
Access Memory Module
The MCM36800 is a dynamic random access memory (DRAM) module organized
as 8,388,608 x 36 bits. The module is a 72–lead single–in–line memory module
(SIMM) consisting of sixteen MCM517400B DRAMs, housed in 300 mil J–lead small
outline packages (SOJ), and eight MCM54100AN DRAMs housed in 300 mil J–lead
small outline packages (SOJ), mounted on a substrate along with a 0.22
µF
(min)
decoupling capacitor mounted adjacent to each DRAM. The MCM517400B is a
CMOS high–speed dynamic random access memory organized as 4,194,304 four–bit
words and fabricated with CMOS silicon–gate process technology.
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Three–State Data Output
Early–Write Common I/O Capability
Fast Page Mode Capability
TTL–Compatible Inputs and Outputs
RAS–Only Refresh
CAS Before RAS Refresh
Hidden Refresh
2048 Cycle Refresh: 32 ms
Consists of Sixteen 4M x 4 DRAMs, Eight 4M x 1 DRAMs, and Twenty–Four
0.22
µF
(Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC): MCM36800–60 = 60 ns (Max)
MCM36800–70 = 70 ns (Max)
Low Active Power Dissipation: MCM36800–60 = 7.61 W (Max)
MCM36800–70 = 6.51 W (Max)
Low Standby Power Dissipation: TTL Levels = 264 mW (Max)
CMOS Levels = 132 mW (Max)
1
AS PACKAGE
SIMM MODULE
CASE 866J–01
TOP VIEW
36
37
PIN ASSIGNMENTS
72
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Name
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
VCC
NC
A0
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Name
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
Pin
25
26
27
28
29
30
31
32
33
34
35
36
Name
DQ24
DQ7
DQ25
A7
NC
VCC
A8
A9
RAS3
RAS2
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
Name
DQ17
DQ35
VSS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
Pin
49
50
51
52
53
54
55
56
57
58
59
60
Name
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
VCC
DQ32
Pin
61
62
63
64
65
66
67
68
69
70
71
72
Name
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
VSS
All power supply and ground pins must be
connected for proper operation of the
device.
PIN NAMES
A0 – A10 . . . . . . . . . . . . . Address Inputs
DQ0 – DQ35 . . . . . . . Data Input/Output
CAS0 – CAS3 Column Address Strobe
PD1 – PD4 . . . . . . . . . Presence Detect
RAS0 – RAS3 . . . Row Address Strobe
W . . . . . . . . . . . . . . . . . Read/Write Input
VCC . . . . . . . . . . . . . . . . . . Power (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . No Connection
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
10/95
©
Motorola, Inc. 1995
MOTOROLA DRAM
MCM36800
1
BLOCK DIAGRAM
CAS0
CAS
RAS
G
I/O1
I/O2
I/O3
A0 – A10 I/O4
DQ4 – DQ7
CAS
RAS
G
I/O1
I/O2
I/O3
A0 – A10 I/O4
DQ8
CAS
RAS
CAS1
CAS
RAS
G
W
Din
Dout
A0 – A10
DQ9 – DQ12
I/O1
I/O2
I/O3
A0 – A10 I/O4
DQ13 – DQ16
CAS
RAS
G
CAS
RAS
CAS2
CAS
RAS
G
I/O1
I/O2
I/O3
A0 – A10 I/O4
I/O1
I/O2
I/O3
A0 – A10 I/O4
Din
Dout
A0 – A10
I/O1
I/O2
I/O3
A0 – A10 I/O4
I/O1
I/O2
I/O3
A0 – A10 I/O4
DQ35
CAS
RAS
W
A0 – A10
VCC
0.22
µF
(MIN)
VSS
PRESENCE DETECT PIN OUT
Pin Name
PD1
PD2
PD3
PD4
60 ns
NC
VSS
NC
NC
70 ns
NC
VSS
VSS
NC
U0 – U23
W
Din
Dout
A0 – A10
Din
Dout A0 – A10
W
CAS
RAS
DQ27 – DQ30
I/O1
I/O2
I/O3
A0 – A10 I/O4
DQ17
W
Din
Dout
A0 – A10
DQ18 – DQ21
Din
Dout A0 – A10
I/O1
I/O2
I/O3
I/O4 A0 – A10
I/O1
I/O2
I/O3
I/O4 A0 – A10
Din
Dout A0 – A10
I/O1
I/O2
I/O3
I/O4 A0 – A10
I/O1
I/O2
I/O3
I/O4 A0 – A10
W
CAS
RAS
CAS
RAS
G
I/O1
I/O2
I/O3
I/O4 A0 – A10
CAS
RAS
G
I/O1
I/O2
I/O3
I/O4 A0 – A10
CAS
RAS
G
Din
Dout A0 – A10
W
CAS
RAS
DQ0 – DQ3
I/O1
I/O2
I/O3
I/O4 A0 – A10
I/O1
I/O2
I/O3
I/O4 A0 – A10
CAS
RAS
G
RAS1
RAS0
W
W
W
W
CAS
RAS
G
W
W
W
W
RAS2
RAS3
W
W
DQ22 – DQ25
CAS
RAS
G
CAS
RAS
CAS3
CAS
RAS
G
W
W
CAS
RAS
G
CAS
RAS
CAS
RAS
G
DQ26
W
W
W
W
DQ31 – DQ34
CAS
RAS
G
CAS
RAS
G
W
W
U0 – U23
MCM36800
2
MOTOROLA DRAM
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Data Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Symbol
VCC
Vin, Vout
Iout
PD
TA
Value
– 1 to + 7
– 1 to + 7
50
16.8
0 to + 70
Unit
V
V
mA
W
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
Tstg
– 55 to + 150
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(All voltages referenced to VSS)
Parameter
Supply Voltage (Operating Voltage Range)
Symbol
VCC
VSS
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
* – 2.0 V at pulse width
≤
20 ns.
VIH
VIL
Min
4.5
0
2.4
– 0.5*
Typ
5.0
0
—
—
Max
5.5
0
VCC + 0.5 V
0.8
V
V
Unit
V
DC CHARACTERISTICS AND SUPPLY CURRENTS
(All voltages referenced to VSS)
Characteristic
VCC Power Supply Current
MCM36800–60, tRC = 110 ns
MCM36800–70, tRC = 130 ns
Symbol
ICC1
ICC2
ICC3
—
—
ICC4(P)
ICC5
ICC6
—
—
Ilkg(I)
Ilkg(O)
VOH
VOL
– 240
– 20
2.4
—
1384
1184
240
20
—
0.4
µA
µA
V
V
—
—
1384
1184
744
24
mA
mA
mA
1
1, 2
Min
—
—
—
Max
1384
1184
48
Unit
mA
mA
mA
1, 2
Notes
1, 2
VCC Power Supply Current (Standby) (RAS = CAS = VIH)
VCC Power Supply Current During RAS–Only Refresh Cycles (CAS = VIH)
MCM36800–60, tRC = 110 ns
MCM36800–70, tRC = 130 ns
VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL)
VCC Power Supply Current (Standby) (RAS = CAS = VCC – 0.2 V)
VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM36800–60, tRC = 110 ns
MCM36800–70, tRC = 130 ns
Input Leakage Current (0 V
≤
Vin
≤
VCC)
Output Leakage Current (0 V
≤
Vout
≤
VCC, Output Disable)
Output High Voltage (IOH = – 5 mA)
Output Low Voltage (IOL = 4.2 mA)
NOTES:
1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
2. Address may be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less during tPC.
CAPACITANCE
(f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance
A0 – A10
W
RAS0 – RAS3, CAS0 – CAS3
DQ0 – DQ7, DQ9 – DQ16, DQ18 – DQ25, DQ27 – DQ34
DQ8, DQ17, DQ26, DQ35
Symbol
Cin
Max
130
178
52
24
34
Unit
pF
I/O Capacitance
CI/O
pF
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I
∆t/∆V.
MOTOROLA DRAM
MCM36800
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ AND WRITE CYCLES
(See Notes 1, 2, 3, and 4)
Symbol
Parameter
Random Read or Write Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from Precharge CAS
CAS to Output in Low–Z
Output Buffer and Turn–Off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
RAS Pulse Width
RAS Hold Time
CAS Hold Time
CAS Precharge to RAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
CAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Setup Time
Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Hold Time Referenced to CAS
Write Command Pulse Width
Std
tRELREL
tRELQV
tCELQV
tAVQV
tCEHQV
tCELQX
tCEHQZ
tT
tREHREL
tRELREH
tCELREH
tRELCEH
tCEHREH
tCELCEH
tRELCEL
tRELAV
tCEHREL
tCEHCEL
tAVREL
tRELAX
tAVCEL
tCELAX
tAVREH
tWHCEL
tCEHWX
tREHWX
tCELWH
tWLWH
Alt
tRC
tRAC
tCAC
tAA
tCPA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tRHCP
tCAS
tRCD
tRAD
tCRP
tCP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
MCM36800–60
Min
110
—
—
—
—
0
0
3
45
60
20
60
40
20
20
15
5
10
0
10
0
15
30
0
0
0
10
10
Max
—
60
20
30
35
—
20
50
—
10 k
—
—
—
10 k
40
30
—
—
—
—
—
—
—
—
—
—
—
—
MCM36800–70
Min
130
—
—
—
—
0
0
3
50
70
20
70
40
20
20
15
5
10
0
10
0
15
35
0
0
0
15
15
Max
—
70
20
35
40
—
20
50
—
10 k
—
—
—
10 k
50
35
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
11
12
Notes
5
6, 7
6, 8
6, 9
6
6
10
NOTES:
(continued)
11.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
12.
An initial pause of 200
µs
is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed.
13.
The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
14.
AC measurements tT = 5.0 ns.
15.
The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (0°C
≤
TA
≤
70°C) is ensured.
16.
Measured with a current load equivalent to 2 TTL (– 200
µA,
+ 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
17.
Assumes that tRCD
≤
t RCD (max).
18.
Assumes that tRCD
≥
t RCD (max).
19.
Assumes that tRAD
≥
t RAD (max).
10. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the t RCD (max) limit ensures that t RAC (max) can be met. t RCD (max) is specified as a reference point only; if t RCD
is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
12. Operation within the t RAD (max) limit ensures that t RAC (max) can be met. t RAD (max) is specified as a reference point only; if t RAD
is greater than the specified tRAD (max), then access time is controlled exclusively by tAA .
13. Either t RRH or t RCH must be satisfied for a read cycle.
MCM36800
4
MOTOROLA DRAM
READ AND WRITE CYCLES
(Continued)
Symbol
Parameter
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Setup Time
Data In Hold Time
Write Command Setup Time
Refresh Period
CAS Setup Time for CAS Before RAS Refresh
CAS Hold Time for CAS Before RAS Refresh
RAS Precharge to CAS Active Time
CAS Precharge Time for CAS Before RAS
Counter Time
Write Command Setup Time (Test Mode)
Write Command Hold Time (Test Mode)
Write to RAS Precharge Time (CAS Before RAS
Refresh)
Write to RAS Hold Time (CAS Before RAS
Refresh)
Fast Page Mode Cycle Time
CAS Precharge to RAS Hold Time (Fast Page
Mode)
RAS Pulse Width (Fast Page Mode)
Std
tWLREH
tWLCEH
tDVCEL
tCELDX
tWLCEL
tRVRV
tRELCEL
tRELCEH
tREHCEL
tCEHCEL
tWLREL
tRELWH
tWHREL
tRELWL
tCELCEL
tCEHREH
tRELREH
Alt
tRWL
tCWL
tDS
tDH
tWCS
tRFSH
tCSR
tCHR
tRPC
tCPT
tWTS
tWTH
tWRP
tWRH
tPC
tRHCP
tRASP
MCM36800–60
Min
20
20
0
15
0
—
5
15
5
30
10
10
10
10
45
35
60
Max
—
—
—
—
—
32
—
—
—
—
—
—
—
—
—
—
200 k
MCM36800–70
Min
20
20
0
15
0
—
5
15
5
40
10
10
10
10
45
40
70
Max
—
—
—
—
—
32
—
—
—
—
—
—
—
—
—
—
200 k
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
14
15
Notes
NOTES:
14. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in late write cycles.
15. t WCS is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if t WCS
≥
t WCS (min),
the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition
is not satisfied, the condition of the data out (at access time) is indeterminate.
MOTOROLA DRAM
MCM36800
5
RF/无线
