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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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by MCM6229BA/D

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MCM6229BA

J PACKAGE

300 MIL SOJ

CASE 810B–03

256K x 4 Bit Static Random

Access Memory

The MCM6229BA is a 1,048,576 bit static random access memory organized

as 262,144 words of 4 bits, fabricated using high–performance silicon–gate

CMOS technology. Static design eliminates the need for external clocks or timing

strobes, while CMOS circuitry reduces power consumption and provides for

greater reliability.

The MCM6229BA is equipped with both chip enable (E) and output enable (G)

pins, allowing for greater system flexibility and eliminating bus contention prob-

lems. Either input, when high, will force the outputs to high impedance.

The MCM6229BA is available in 300 mil and 400 mil, 28–lead surface–mount

SOJ packages.

•

Single 5 V

10% Power Supply

Fast Access Times: 15/17/20/25/35 ns

Equal Address and Chip Enable Access Times

All Inputs and Outputs are TTL Compatible

Three–State Outputs

Low Power Operation: 120/115/110/105/100 mA Maximum, Active AC

BLOCK DIAGRAM

A17

A15

A14

ROW

DECODER

MEMORY MATRIX

512 ROWS x

2048 COLUMNS

WJ PACKAGE

400 MIL SOJ

CASE 810–03

PIN ASSIGNMENT

A10

VSS

VCC

A17

A16

A15

A14

A13

A12

A11

NC*

DQ3

DQ2

DQ1

DQ0

PIN NAMES

A0 – A17 . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

DQ0 – DQ3 . . . . . . Data Inputs/Outputs

VCC . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

NC* . . . . . . . . . . . . . . . . . No Connection

*If not used for no connect, then do not ex-

ceed voltages of – 0.5 to VCC + 0.5 V.

This pin is used for manufacturing diag-

nostics.

DQ0

INPUT

DATA

CONTROL

DQ3

A10

COLUMN I/O

COLUMN DECODER

A16 A11 A12 A13

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

5/95

Motorola, Inc. 1995

MOTOROLA FAST SRAM

MCM6229BA

3–1

TRUTH TABLE

Mode

Not Selected

Output Disabled

Read

Write

I/O Pin

High–Z

Dout

Din

Cycle

—

Read

Write

Current

ISB1, ISB2

ICCA

H = High, L = Low, X = Don’t Care

ABSOLUTE MAXIMUM RATINGS

(See Note)

Rating

Power Supply Voltage Relative to VSS

Voltage Relative to VSS for Any Pin

Except VCC

Output Current (per I/O)

Power Dissipation

Temperature Under Bias

Operating Temperature

Storage Temperature

Symbol

VCC

Vin, Vout

Iout

Tbias

Value

– 0.5 to 7.0

– 0.5 to VCC + 0.5

1.0

– 10 to + 85

0 to + 70

Unit

°C

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to these high–impedance

circuits.

This CMOS memory circuit has been de-

signed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established. The circuit is in a test

socket or mounted on a printed circuit board

and transverse air flow of at least 500 linear feet

per minute is maintained.

Tstg

– 55 to + 150

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V

10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range)

Input High Voltage

Input Low Voltage

* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width

≤

20 ns).

** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width

≤

20 ns).

Symbol

VCC

VIH

VIL

Min

4.5

2.2

– 0.5*

Max

5.5

VCC + 0.3**

0.8

Unit

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Output Leakage Current (E = VIH, Vout = 0 to VCC)

AC Active Supply Current (Iout = 0 mA, all inputs =

VIL or VIH, VIL = 0, VIH

≥

3 V, cycle time

≥

tAVAV min,

VCC = max)

MCM6229BA–15: tAVAV = 15 ns

MCM6229BA–17: tAVAV = 17 ns

MCM6229BA–20: tAVAV = 20 ns

MCM6229BA–25: tAVAV = 25 ns

MCM6229BA–35: tAVAV = 35 ns

MCM6229BA–15: tAVAV = 15 ns

MCM6229BA–17: tAVAV = 17 ns

MCM6229BA–20: tAVAV = 20 ns

MCM6229BA–25: tAVAV = 25 ns

MCM6229BA–35: tAVAV = 35 ns

Symbol

Ilkg(I)

Ilkg(O)

ICCA

Min

—

2.4

Max

135

120

115

110

100

0.4

—

Unit

µA

AC Standby Current (VCC = max, E = VIH, f = fmax)

ISB1

CMOS Standby Current (E

≥

VCC – 0.2 V, Vin

≤

VSS + 0.2 V

≥

VCC – 0.2 V, VCC = max, f = 0 MHz)

Output Low Voltage (IOL = + 8.0 mA)

Output High Voltage (IOH = – 4.0 mA)

ISB2

VOL

VOH

MCM6229BA

3–2

MOTOROLA FAST SRAM

CAPACITANCE

(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic

Input Capacitance

Input/Output Capacitance

All Inputs except Clocks & DQs

E, G, and W

Symbol

Cin

Cck

CI/O

Typ

Max

Unit

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V

10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns

Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V

Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A

READ CYCLE TIMING

(See Notes 1 and 2)

6229BA–15

Parameter

Read Cycle Time

Address Access Time

Enable Access Time

Output Enable Access

Time

Output Hold from

Address Change

Enable Low to Output

Active

Output Enable Low to

Output Active

Enable High to Output

High–Z

Output Enable High to

Output High–Z

Symbol

tAVAV

tAVQV

tELQV

tGLQV

tAXQX

tELQX

tGLQX

tEHQZ

tGHQZ

Min

—

Max

—

6229BA–17

Min

—

Max

—

6229BA–20

Min

—

Max

—

6229BA–25

Min

—

Max

—

6229BA–35

Min

—

Max

—

Unit

5, 6 ,7

5, 6, 7

Notes

2, 3

NOTES:

1. W is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-

tention conditions during read and write cycles.

3. All timings are referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E going low.

5. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device

and from device to device.

6. Transition is measured

500 mV from steady–state voltage with load of Figure 1B.

7. This parameter is sampled and not 100% tested.

8. Device is continuously selected (E

≤

VIL, G

≤

VIL).

AC TEST LOADS

+5 V

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

OUTPUT

255

Ω

5 pF

480

Ω

TIMING LIMITS

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time (even though most devices do not

require it). On the other hand, responses from

the memory are specified from the device

point of view. Thus, the access time is shown

as a maximum since the device never pro-

vides data later than that time.

Figure 1A

Figure 1B

MOTOROLA FAST SRAM

MCM6229BA

3–3

READ CYCLE 1

(See Notes 1, 2, and 8)

tAVAV

A (ADDRESS)

tAXQX

Q (DATA OUT)

PREVIOUS DATA VALID

tAVQV

DATA VALID

READ CYCLE 2

(See Note 8)

tAVAV

A (ADDRESS)

tELQV

E (CHIP ENABLE)

tELQX

G (OUTPUT ENABLE)

tGLQV

tGLQX

Q (DATA OUT)

HIGH–Z

tAVQV

tELICCH

ICC

SUPPLY CURRENT

ISB

tEHICCL

DATA VALID

tGHQZ

tEHQZ

MCM6229BA

3–4

MOTOROLA FAST SRAM

WRITE CYCLE 1

(W Controlled, See Notes 1, 2, and 3)

6229BA–15

Parameter

Write Cycle Time

Address Setup Time

Address Valid to End of

Write

Write Pulse Width

Data Valid to End of

Write

Data Hold TIme

Write Low to Data

High–Z

Write High to Output

Active

Write Recovery Time

Symbol

tAVAV

tAVWL

tAVWH

tWLWH,

tWLEH

tDVWH

tWHDX

tWLQZ

tWHQX

tWHAX

Min

Max

—

6229BA–17

Min

Max

—

6229BA–20

Min

Max

—

6229BA–25

Min

Max

—

6229BA–35

Min

Max

—

Unit

5, 6, 7

Notes

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten-

tion conditions during read and write cycles.

3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. All timings are referenced from the last valid address to the first transitioning address.

5. Transition is measured

500 mV from steady–state voltage with load of Figure 1B.

6. This parameter is sampled and not 100% tested.

7. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.

WRITE CYCLE 1

(W Controlled See Notes 1, 2, and 3)

tAVAV

A (ADDRESS)

tAVWH

E (CHIP ENABLE)

tWLWH

tWLEH

W (WRITE ENABLE)

tAVWL

D (DATA IN)

tWLQZ

Q (DATA OUT)

HIGH–Z

tDVWH

DATA VALID

tWHQX

tWHDX

tWHAX

MOTOROLA FAST SRAM

MCM6229BA

3–5

参数对比

与MCM6229BAWJ25相近的元器件有：MCM6229BAWJ15、MCM6229BAJ35、MCM6229BAWJ17、MCM6229BAJ17、MCM6229BAJ25、MCM6229BAJ15、MCM6229BAWJ20、MCM6229BAWJ35、MCM6229BAJ20。描述及对比如下：

型号	MCM6229BAWJ25	MCM6229BAWJ15	MCM6229BAJ35	MCM6229BAWJ17	MCM6229BAJ17	MCM6229BAJ25	MCM6229BAJ15	MCM6229BAWJ20	MCM6229BAWJ35	MCM6229BAJ20
描述	Standard SRAM, 256KX4, 25ns, CMOS, PDSO28, 0.400 INCH, SOJ-28	Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.400 INCH, SOJ-28	Standard SRAM, 256KX4, 35ns, CMOS, PDSO28, 0.300 INCH, SOJ-28	Standard SRAM, 256KX4, 17ns, CMOS, PDSO28, 0.400 INCH, SOJ-28	Standard SRAM, 256KX4, 17ns, CMOS, PDSO28, 0.300 INCH, SOJ-28	Standard SRAM, 256KX4, 25ns, CMOS, PDSO28, 0.300 INCH, SOJ-28	Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.300 INCH, SOJ-28	Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.400 INCH, SOJ-28	Standard SRAM, 256KX4, 35ns, CMOS, PDSO28, 0.400 INCH, SOJ-28	Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.300 INCH, SOJ-28
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
包装说明	0.400 INCH, SOJ-28	0.400 INCH, SOJ-28	0.300 INCH, SOJ-28	0.400 INCH, SOJ-28	0.300 INCH, SOJ-28	0.300 INCH, SOJ-28	0.300 INCH, SOJ-28	0.400 INCH, SOJ-28	0.400 INCH, SOJ-28	0.300 INCH, SOJ-28
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknow
ECCN代码	EAR99	3A991.B.2.B	EAR99	3A991.B.2.B	3A991.B.2.B	EAR99	3A991.B.2.B	3A991.B.2.B	EAR99	3A991.B.2.B
最长访问时间	25 ns	15 ns	35 ns	17 ns	17 ns	25 ns	15 ns	20 ns	35 ns	20 ns
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28	R-PDSO-J28
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
长度	18.415 mm	18.415 mm	18.415 mm	18.415 mm	18.415 mm	18.415 mm	18.415 mm	18.415 mm	18.415 mm	18.415 mm
内存密度	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bi
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
内存宽度	4	4	4	4	4	4	4	4	4	4
功能数量	1	1	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1	1	1
端子数量	28	28	28	28	28	28	28	28	28	28
字数	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
字数代码	256000	256000	256000	256000	256000	256000	256000	256000	256000	256000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	256KX4	256KX4	256KX4	256KX4	256KX4	256KX4	256KX4	256KX4	256KX4	256KX4
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
可输出	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ	SOJ
封装等效代码	SOJ28,.44	SOJ28,.44	SOJ28,.34	SOJ28,.44	SOJ28,.34	SOJ28,.34	SOJ28,.34	SOJ28,.44	SOJ28,.44	SOJ28,.34
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
电源	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.75 mm	3.75 mm	3.75 mm	3.75 mm	3.75 mm	3.75 mm	3.75 mm	3.75 mm	3.75 mm	3.75 mm
最大待机电流	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A
最小待机电流	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
最大压摆率	0.11 mA	0.135 mA	0.1 mA	0.12 mA	0.12 mA	0.11 mA	0.135 mA	0.115 mA	0.1 mA	0.115 mA
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
宽度	10.16 mm	10.16 mm	7.62 mm	10.16 mm	7.62 mm	7.62 mm	7.62 mm	10.16 mm	10.16 mm	7.62 mm
厂商名称	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	-	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )