MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MCM6229BB
XJ PACKAGE
400 MIL SOJ
CASE 810–03
256K x 4 Bit Static Random
Access Memory
The MCM6229BB is a 1,048,576 bit static random access memory organized
as 262,144 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6229BB is equipped with both chip enable (E) and output enable (G)
pins, allowing for greater system flexibility and eliminating bus contention problems.
The MCM6229BB is available in 300 mil and 400 mil, 28 lead surface–mount
SOJ packages.
•
•
•
•
•
•
Single 5 V
±
10% Power Supply
Fast Access Times: 15/17/20/25/35 ns
Equal Address and Chip Enable Access Times
All Inputs and Outputs are TTL Compatible and LVTTL Compatible
Three State Outputs
Low Power Operation: 155/150/135/130/110 mA Maximum, Active AC
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
512 ROWS x
2048 COLUMNS
EJ PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENTS
A
A
A
A
A
A
A
A
A
A
A
E
G
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A
A
A
A
A
A
A
NC*
DQ
DQ
DQ
DQ
W
DQ
INPUT
DATA
CONTROL
DQ
A
A
A
COLUMN I/O
COLUMN DECODER
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . Data Inputs/Outputs
VCC . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC* . . . . . . . . . . . . . . . . . No Connection
*If not used for no connect, then do not ex-
ceed voltages of – 0.5 to VCC + 0.5 V.
This pin is used for manufacturing diag-
nostics.
A
A
A
A
A
A
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
11/7/96
©
Motorola, Inc. 1995
MOTOROLA FAST SRAM
MCM6229BB
1
TRUTH TABLE
E
H
L
L
L
G
X
H
L
X
W
X
H
H
L
Mode
Not Selected
Output Disabled
Read
Write
I/O Pin
High–Z
High–Z
Dout
Din
Cycle
—
—
Read
Write
Current
ISB1, ISB2
ICCA
ICCA
ICCA
H = High, L = Low, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin
Except VCC
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature
Symbol
VCC
Vin, Vout
Iout
PD
Tbias
TA
Value
– 0.5 to 7.0
– 0.5 to VCC + 0.5
±
20
1.0
– 10 to + 85
0 to + 70
Unit
V
V
mA
W
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
Tstg
– 55 to + 150
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
20 ns).
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width
≤
20 ns).
Symbol
VCC
VIH
VIL
Min
4.5
2.2
– 0.5*
Max
5.5
VCC + 0.3**
0.8
Unit
V
V
V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Output Leakage Current (E = VIH, Vout = 0 to VCC)
AC Active Supply Current (Iout = 0 mA, all inputs =
VIL or VIH, VIL = 0, VIH
≥
3 V, cycle time
≥
tAVAV min,
VCC = max)
MCM6229BB–15: tAVAV = 15 ns
MCM6229BB–17: tAVAV = 17 ns
MCM6229BB–20: tAVAV = 20 ns
MCM6229BB–25: tAVAV = 25 ns
MCM6229BB–35: tAVAV = 35 ns
MCM6229BB–15: tAVAV = 15 ns
MCM6229BB–17: tAVAV = 17 ns
MCM6229BB–20: tAVAV = 20 ns
MCM6229BB–25: tAVAV = 25 ns
MCM6229BB–35: tAVAV = 35 ns
Symbol
Ilkg(I)
Ilkg(O)
ICCA
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
Max
±
1
±
1
155
150
135
130
110
45
40
35
30
25
5
0.4
—
Unit
µA
µA
mA
AC Standby Current (VCC = max, E = VIH, f = fmax)
ISB1
mA
CMOS Standby Current (E
≥
VCC – 0.2 V, Vin
≤
VSS + 0.2 V
or
≥
VCC – 0.2 V, VCC = max, f = 0 MHz)
Output Low Voltage (IOL = + 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
ISB2
VOL
VOH
mA
V
V
MCM6229BB
2
MOTOROLA FAST SRAM
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance
I/O Capacitance
All Inputs Except Clocks and DQs
E, G, and W
DQ
Symbol
Cin
Cck
CI/O
Typ
4
5
5
Max
6
8
8
Unit
pF
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING
(See Notes 1, 2, and 3)
6229BB–15
Parameter
Read Cycle Time
Address Access Time
Enable Access Time
Output Enable Access Time
Output Hold from Address
Change
Enable Low to Output Active
Output Enable Low to Output
Active
Enable High to Output High–Z
Output Enable High to Output
High–Z
Symbol
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
Min
15
—
—
—
3
5
0
0
0
Max
—
15
15
6
—
—
—
6
6
6229BB–17
Min
17
—
—
—
3
5
0
0
0
Max
—
17
17
7
—
—
—
7
7
6229BB–20
Min
20
—
—
—
3
5
0
0
0
Max
—
20
20
7
—
—
—
7
7
6229BB–25
Min
25
—
—
—
3
5
0
0
0
Max
—
25
25
8
—
—
—
8
8
6229BB–35
Min
35
—
—
—
3
5
0
0
0
Max
—
35
35
8
—
—
—
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
5, 6, 7
5, 6, 7
5, 6, 7
5, 6, 7
4
Notes
3
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device
and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤
VIL, G
≤
VIL).
+5 V
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
OUTPUT
255
Ω
5 pF
480
Ω
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
(a)
(b)
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM6229BB
3
READ CYCLE 1
(See Notes 1, 2, 3, and 9)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
tAVQV
DATA VALID
READ CYCLE 2
(See Notes 3 and 5)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tELQX
G (OUTPUT ENABLE)
tGLQV
tGLQX
Q (DATA OUT)
HIGH–Z
tAVQV
tELICCH
ICC
SUPPLY CURRENT
ISB
tEHICCL
DATA VALID
tGHQZ
tEHQZ
MCM6229BB
4
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, 3, and 4)
6229BB–15
Parameter
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold TIme
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
Symbol
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
Min
15
0
12
12
7
0
—
5
0
Max
—
—
—
—
—
—
6
—
—
6229BB–17
Min
17
0
14
14
8
0
—
5
0
Max
—
—
—
—
—
—
7
—
—
6229BB–20
Min
20
0
15
15
9
0
—
5
0
Max
—
—
—
—
—
—
7
—
—
6229BB–25
Min
25
0
17
17
10
0
—
5
0
Max
—
—
—
—
—
—
8
—
—
6229BB–35
Min
35
0
20
20
11
0
—
5
0
Max
—
—
—
—
—
—
8
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
5, 6, 7
5, 6, 7
Notes
4
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
(W Controlled See Notes 1, 2, 3, and 4)
tAVAV
A (ADDRESS)
tAVWH
E (CHIP ENABLE)
tWLWH
tWLEH
W (WRITE ENABLE)
tAVWL
D (DATA IN)
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tDVWH
DATA VALID
tWHQX
tWHDX
tWHAX
MOTOROLA FAST SRAM
MCM6229BB
5
