MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6949/D
1M x 4 Bit Static Random
Access Memory
The MCM6949 is a 4,194,304–bit static random access memory organized as
1,048,576 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6949 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.
The MCM6949 is available in a 400 mil, 32–lead surface–mount SOJ package.
MCM6949
Freescale Semiconductor, Inc...
•
•
•
•
•
•
Single 3.3 V – 5%, + 10% Power Supply
Fast Access Time: 8/10/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
Power Operation: 195/165/160/155 mA Maximum, Active AC
CH
AR
ED
IV
BY
EE
FR
LE
CA
S
S
CO
I
M
E
,I
OR
PIN NAMES
CT
A0 – A19 . . . . . . . . . . . . . . . . Address Inputs
DU
. . . . . . . . . . . . . . . . . . . . . . . Write Enable
N
W
C.
N
YJ PACKAGE
400 MIL SOJ
CASE 857A–02
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . . . . . No Connection
VDD . . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 9
5/20/99
©
Motorola, Inc. 1999
MOTOROLA FAST SRAM
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MCM6949
1
Freescale Semiconductor, Inc.
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
Freescale Semiconductor, Inc...
DQ
INPUT
DATA
CONTROL
DQ
E
W
G
CH
AR
ED
IV
BY
LE
A
C
A
A
A
ES
RE
F
,I
OR
CT
U
COLUMN I/O
D
ON
COLUMN DECODER
IC
M
SE
A
A
A
A
A
A
A
C.
N
DQ
DQ
PIN ASSIGNMENT
A
A
A
A
A
E
DQ
VDD
VSS
DQ
W
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
A
G
DQ
VSS
VDD
DQ
A
A
A
A
A
NC
MCM6949
2
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TRUTH TABLE
(X = Don’t Care)
E
H
L
L
L
G
X
H
L
X
W
X
H
H
L
Mode
Not Selected
Output Disabled
Read
Write
I/O Pin
High–Z
High–Z
Dout
High–Z
Cycle
—
—
Read
Write
Current
ISB1, ISB2
IDDA
IDDA
IDDA
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin
Except VDD
Output Current (per I/O)
Power Dissipation
Symbol
VDD
Vin, Vout
Iout
PD
Tbias
TA
Tstg
Value
– 0.5 to + 5.0
– 0.5 to VDD + 0.5
±
20
1.0
– 10 to + 85
0 to + 70
– 55 to + 150
Unit
V
V
mA
W
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
Freescale Semiconductor, Inc...
Temperature Under Bias
Operating Temperature
Storage Temperature — Plastic
S
E
RATINGS are
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
AL
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
SC
extended periods of time could affect device reliability.
EE
FR
Y
DC OPERATING CONDITIONS AND CHARACTERISTICS
B
5%, + 10%, T = 0 to + 70°C, Unless Otherwise Noted)
(VDD = 3.3 V –
A
ED
V
RECOMMENDED OPERATING
I
CONDITIONS
CH
Parameter
Symbol
Min
Typ
AR
Supply Voltage (Operating Voltage Range)
Input High Voltage
Input Low Voltage
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
2.0 ns).
VDD
VIH
VIL
3.135
2.2
– 0.5
*
3.3
—
—
CO
I
M
°C
E
°C
°C
,I
OR
CT
DU
N
C.
N
Max
3.63
VDD + 0.3
0.8
Unit
V
V
V
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Output Low Voltage (IOL = + 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
Symbol
Ilkg(I)
Ilkg(O)
VOL
VOH
Min
—
—
—
2.4
Max
±
1.0
±
1.0
0.4
—
Unit
µA
µA
V
V
POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current
(Iout = 0 mA, VDD = Max)
MCM6949–8: tAVAV = 8 ns
MCM6949–10: tAVAV = 10 ns
MCM6949–12: tAVAV = 12 ns
MCM6949–15: tAVAV = 15 ns
MCM6949–8: tAVAV = 8 ns
MCM6949–10: tAVAV = 10 ns
MCM6949–12: tAVAV = 12 ns
MCM6949–15: tAVAV = 15 ns
Symbol
IDD
0 to + 70°C
195
165
160
155
55
50
50
45
20
Unit
mA
AC Standby Current (VDD = Max, E = VIH,
No Other Restrictions on Other Inputs)
ISB1
mA
CMOS Standby Current (E
≥
VDD – 0.2 V, Vin
≤
VSS + 0.2 V or
≥
VDD – 0.2 V)
(VDD = Max, f = 0 MHz)
ISB2
mA
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MCM6949
3
Freescale Semiconductor, Inc.
CAPACITANCE
(f = 1.0 MHz, dV = 3.3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
Input/Output Capacitance
All Inputs Except Clocks and DQs
E, G, W
DQ
Symbol
Cin
Cck
CI/O
Typ
4
5
5
Max
6
8
8
Unit
pF
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V – 5%, + 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING
(See Notes 1 and 2)
Freescale Semiconductor, Inc...
Parameter
P
Read Cycle Time
Address Access Time
Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Symbol
S b l
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
ED
tEHQZ
IV
tGHQZ
Output Enable High to Output High–Z
CH
NOTES:
AR
1. W is high for read cycle.
BY
F
,I
OR
MCM6949–15
MCM6949–8 MCM6949–10 MCM6949–12
CT
Min
Max
Min
Max
Min
U
Max
Min
Max
D
N
12
8
—
10
—
O
—
15
—
C
I
—
8
—
M
10
—
12
—
15
E
S
—
8
10
—
12
—
15
E
—
—
4
5
—
6
—
7
AL
—
C
2
S
—
2
—
2
—
2
—
EE
—
3
—
3
—
3
—
R
3
0
0
0
—
4
4
0
0
0
—
5
5
0
0
0
—
6
6
0
0
0
—
7
7
C.
N
Unit
U i
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
N
3
4
5, 6, 7
5, 6, 7
5, 6, 7
5, 6, 7
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device
to device.
6. Transition is measured
±
200 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤
VIL, G
≤
VIL).
t
t
TIMING LIMITS
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1. AC Test Load
MCM6949
4
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Freescale Semiconductor, Inc.
READ CYCLE 1
(See Note 8)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
tAVQV
DATA VALID
READ CYCLE 2
(See Note 4)
tAVAV
Freescale Semiconductor, Inc...
A (ADDRESS)
tELQV
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT)
HIGH–Z
SUPPLY CURRENT
IDD
ISB
CH
AR
ED
IV
BY
S
E
tELQX
L
CA
ES
tGLQV
RE
F
tGLQX
tAVQV
CO
I
M
E
,I
OR
CT
DU
N
C.
N
tEHQZ
tGHQZ
DATA VALID
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MCM6949
5
嵌入式系统
