MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MCM69F536C/D
32K x 36 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
MCM69F536C
Freescale Semiconductor, Inc...
The MCM69F536C is a 1M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 32K
words of 36 bits each. This device integrates input registers, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
R,
count in cache data RAM applications. Synchronous design allows precise cycle
TO
control with the use of an external clock (K). BiCMOS circuitry reduces the overall
UC
power consumption of the integrated functions for greater reliability.
ND
Addresses (SA), data inputs (DQx), and all control signals except output
CO
I
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
M
positive–edge–triggered noninverting registers.
SE
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
E
addresses can be generated internally by the MCM69F536C
L
(burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
CA
controlled by the burst address advance (ADV) input pin.
ES
Write cycles are internally self–timed and are initiated by the rising edge of the
RE
write pulse generation
clock (K) input. This feature eliminates complex
F
off–chip
Y
and provides increased timing flexibility for incoming signals.
B
Synchronous byte write (SBx), synchronous global write (SGW), and
D
E
synchronous write enable SW are provided to allow writes to either individual
IV
are designated as “a”, “b”, “c”, and “d”. SBa
bytes or to all bytes. The four bytes
H
controls DQa, SBb controls
C
DQb, and so on. Individual bytes are written if the
AR
selected byte writes SBx are asserted with SW. All bytes are written if either SGW
is asserted or if all SBx and SW are asserted.
For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array.
The MCM69F536C operates from a 3.3 V power supply and all inputs and
outputs are LVTTL compatible.
•
MCM69F536C–7.5 = 7.5 ns Access / 12 ns Cycle
MCM69F536C–8 = 8 ns Access / 12 ns Cycle
MCM69F536C–8.5 = 8.5 ns Access / 12 ns Cycle
MCM69F536C–9 = 9 ns Access / 12 ns Cycle
MCM69F536C–10 = 10 ns Access / 15 ns Cycle
MCM69F536C–12 = 12 ns Access / 16.6 ns Cycle
•
Single 3.3 V + 10%, – 5% Power Supply
•
ADSP, ADSC, and ADV Burst Control Pins
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Internally Self–Timed Write Cycle
•
Byte Write and Global Write Control
•
5 V Tolerant on all Pins (Inputs and I/Os)
•
100–Pin TQFP Package
I
C.
N
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
REV 5
3/23/99
©
Motorola, Inc. 1999
MOTOROLA FAST SRAM
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MCM69F536C
1
Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
ADSP
K2
BURST
COUNTER
CLR
2
2
15
32K x 36 ARRAY
SA
SA1
SA0
ADDRESS
REGISTER
15
13
SGW
SW
WRITE
REGISTER
a
Freescale Semiconductor, Inc...
SBa
SBb
SBc
CH
AR
ED
IV
BY
EE
FR
LE
CA
S
WRITE
REGISTER
b
S
CO
I
M
E
,I
OR
CT
DU
N
C.
N
36
36
4
DATA–IN
REGISTER
K
WRITE
REGISTER
c
SBd
WRITE
REGISTER
d
K2
SE1
SE2
SE3
G
ENABLE
REGISTER
DQa – DQd
MCM69F536C
2
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
PIN ASSIGNMENT
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
VDD
VSS
K
SGW
SW
G
ADSC
ADSP
ADV
SA
SA
DQc
DQc
DQc
VDD
VSS
DQc
DQc
DQc
DQc
VSS
VDD
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDD
VSS
DQd
DQd
DQd
DQd
VSS
VDD
DQd
DQd
DQd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
78
3
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Freescale Semiconductor, Inc...
CH
AR
ED
IV
BY
EE
FR
LE
CA
S
S
CO
I
M
E
,I
OR
CT
DU
N
DQb
DQb
DQb
VDD
VSS
DQb
DQb
DQb
DQb
VSS
VDD
DQb
DQb
VSS
NC
VDD
NC
DQa
DQa
VDD
VSS
DQa
DQa
DQa
DQa
VSS
VDD
DQa
DQa
DQa
C.
N
MOTOROLA FAST SRAM
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LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
NC
NC
MCM69F536C
3
Freescale Semiconductor, Inc.
PIN DESCRIPTIONS
Pin Locations
85
84
Symbol
ADSC
ADSP
Type
Input
Input
Description
Synchronous Address Status Controller: Initiates READ, WRITE, or
chip deselect cycle.
Synchronous Address Status Processor: Initiates READ, WRITE, or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
83
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86
ADV
DQx
Input
I/O
Freescale Semiconductor, Inc...
89
31
32, 33, 34, 35, 44, 45, 46,
47, 48, 81, 82, 99, 100
36, 37
93, 94, 95, 96
(a) (b) (c) (d)
98
CH
AR
ED
IV
,I
OR
CT
K
Input
Clock: This signal registers the address, data in, and all control signals
DU
except G and LBO.
N
CO
This pin must remain in steady state (this
I
LBO
Input
Linear Burst Order Input:
M
signal not registered or latched). It must be tied high or low.
SE
Low — linear burst count (68K/PowerPC).
High — interleaved burst count (486/i960/Pentium).
LE
CA
SA
Input
Synchronous Address Inputs: These inputs are registered and must
ES
meet setup and hold times.
RE
Input Synchronous Address Inputs: These pins must be wired to the two
F
SA1, SA0
Y
LSBs of the address bus for proper burst operation. These inputs are
B
registered and must meet setup and hold times.
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
SBx
SE1
Input
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Power Supply: 3.3 V + 10%, – 5%.
Ground.
No Connection: There is no connection to the chip. For compatibility
reasons, it is recommended that this pin be tied low for system designs
that do not have a sleep mode associated with the cache/memory
controller. Other vendors’ RAMs may have implemented this Sleep
Mode (ZZ) feature.
No Connection: There is no connection to the chip.
C.
N
97
92
88
SE2
SE3
SGW
Input
Input
Input
87
SW
Input
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
5, 10, 17, 21, 26, 40, 55,
60, 67, 71, 76, 90
64
VDD
VSS
NC
Supply
Supply
Input
14, 16, 38, 39, 42, 43, 49, 50, 66
NC
—
MCM69F536C
4
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TRUTH TABLE
(See Notes 1 through 4)
Next Cycle
Deselect
Deselect
Deselect
Deselect
Deselect
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Address
Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
SE1
1
0
0
X
X
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
SE2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
X
X
1
SE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
CO
I
M
1
E
1
1
0
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
G3
X
X
X
X
X
0
0
1
0
1
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
DQ
High–Z
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
Write 2, 4
X
X
X
X
X
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
Freescale Semiconductor, Inc...
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
NOTES:
,I
0
0
OR
T
1
1
UC
0
1
ND
1
1
1
1
X
0
0
1
1
0
X
X
X
X
X
X
.
C
DQ
N
1
X
X
X
1
1
X
High–Z
WRITE
ED
= logic low.
1. X = Don’t Care. 1 = logic
V
0
I
high.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
CH
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
AR
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
BY
EE
X
FR
X
X
LE
X
0
CA
1
S
1
1
X
S
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X10
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X00
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
Read
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write All Bytes
SGW
H
H
H
H
H
H
H
L
SW
H
L
L
L
L
L
L
X
SBa
X
H
L
H
H
H
L
X
SBb
X
H
H
L
H
H
L
X
SBc
X
H
H
H
L
H
L
X
SBd
X
H
H
H
H
L
L
X
MOTOROLA FAST SRAM
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MCM69F536C
5
