MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MCM69P735
128K x 36 Bit Pipelined
BurstRAM™ Synchronous
Fast Static RAM
The MCM69P735 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC™ and other
high performance microprocessors. It is organized as 128K words of 36 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and a high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P735 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P735 operates from a 3.3 V core power supply and all outputs
operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
•
MCM69P735 Speed Options
Speed
200 MHz
180 MHz
166 MHz
tKHKH
5 ns
5.5 ns
6 ns
Pipelined
tKHQV
2.5 ns
3.0 ns
3.5 ns
Setup
0.5 ns
0.5 ns
0.5 ns
Hold
1 ns
1 ns
1 ns
IDD
475 mA
450 mA
425 mA
Pkg
PBGA
PBGA
PBGA
ZP PACKAGE
PBGA
CASE 999–01
•
3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O
Supply
•
ADSP, ADSC, and ADV Burst Control Pins
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Single–Cycle Deselect Timing
•
Internally Self–Timed Write Cycle
•
Byte Write and Global Write Control
•
PB1 Version 2.0 Compatible
•
JEDEC Standard 119–Pin PBGA Package
BurstRAM is a trademark of Motorola, Inc.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
6/10/97
©
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM69P735
1
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
ADSP
K2
BURST
COUNTER
CLR
2
2
17
128K x 36
ARRAY
SA
SA1
SA0
ADDRESS
REGISTER
17
15
SGW
SW
WRITE
REGISTER
a
36
36
SBa
SBb
WRITE
REGISTER
b
4
WRITE
REGISTER
c
DATA–IN
REGISTER
K
DATA–OUT
REGISTER
SBc
SBd
WRITE
REGISTER
d
K2
K
SE1
SE2
SE3
G
ENABLE
REGISTER
ENABLE
REGISTER
DQa – DQd
MCM69P735
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
1
A
B
C
D
E
DQc
F
G
DQc
H
J
K
L
DQd
M
VDDQ DQd
N
P
R
T
NC
U
VDDQ
NC
NC
SA
NC
SA
NC
SA
NC
NC
NC
NC VDDQ
DQd
DQd
NC
DQd
DQd
SA
VSS
VSS
VSS
LBO
SW
SA1
SA0
VDD
VSS
VSS
VSS
NC
DQa VDDQ
DQa
DQa
SA
DQa
DQa
NC
DQd
SBd
NC
SBa
DQa
DQa
DQc
DQc
DQc
SBc
VSS
NC
VSS
ADV
SGW
VDD
K
SBb
VSS
NC
VSS
DQb
DQb
DQb
DQb
DQc
VSS
VSS
SE1
G
VSS
VSS
DQb
DQb
VDDQ DQc
DQb VDDQ
VDDQ
NC
NC
DQc
2
SA
SE2
SA
DQc
3
SA
SA
SA
VSS
4
ADSP
ADSC
VDD
NC
5
SA
SA
SA
VSS
6
SA
SE3
SA
DQb
7
VDDQ
NC
NC
DQb
VDDQ VDD
DQd
DQd
VDD VDDQ
DQa
DQa
TOP VIEW 119 BUMP PBGA
Not to Scale
MOTOROLA FAST SRAM
MCM69P735
3
PBGA PIN DESCRIPTIONS
Pin Locations
4B
Symbol
ADSC
Type
Input
Description
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address used to initiate a new
READ or chip deselect (exception — chip deselect does not occur
when ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
4A
ADSP
Input
4G
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F
ADV
DQx
Input
I/O
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
4K
3R
K
LBO
Input
Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 3T, 4T, 5T
4N, 4P
SA
SA1, SA0
Input
Input
5L, 5G, 3G, 3L
(a) (b) (c) (d)
4E
SBx
SE1
Input
Input
2B
6B
4H
SE2
SE3
SGW
Input
Input
Input
4M
SW
Input
4C, 2J, 4J, 6J, 4R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P
1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 7T, 2U, 3U, 4U, 5U, 6U
VDD
VDDQ
VSS
NC
Supply
Supply
Supply
—
MCM69P735
4
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 Through 5)
Next Cycle
Deselect
Deselect
Deselect
Deselect
Deselect
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
Address
Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
External
Next
Next
Current
Current
SE1
1
0
0
X
X
0
0
X
X
1
1
X
X
1
1
0
X
1
X
1
SE2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
1
X
X
X
X
SE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
0
X
X
X
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
0
0
1
1
G3
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
X
X
X
X
X
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
High–Z
High–Z
High–Z
High–Z
Write 2, 4
X
X
X
X
X
X5
READ5
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
NOTES:
1. X = don’t care. 1 = logic high. 0 = logic low.
2. Write is defined as either (a) any SBx and SW low or (b) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X10
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X00
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
Read
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write All Bytes
SGW
H
H
H
H
H
H
H
L
SW
H
L
L
L
L
L
L
X
SBa
X
H
L
H
L
H
L
X
SBb
X
H
H
L
H
L
L
X
SBc
X
H
H
H
L
H
L
X
SBd
X
H
H
H
H
L
L
X
MOTOROLA FAST SRAM
MCM69P735
5
