MCP19114/5
Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller
Features
• Input Voltage: 4.5V to 42V
• Can be Configured with Multiple Topologies
Including but not Limited to:
- Flyback
-
Ćuk
- Boost
- SEPIC (Single-Ended Primary-Inductor
Converter)
• Capable of Quasi-Resonant or Fixed-Frequency
Operation
• Low Quiescent Current: 5 mA Typical
• Low Sleep Current: 30 µA Typical
• Low-Side Gate Drivers:
- +5V gate drive
- 0.5A sink/source current
- +10V gate drive
- 1A sink/source current
• Peak Current Mode Control
• Differential Remote Output Sense
• Multiple Output Systems:
- Master or Slave
• AEC-Q100 Qualified
• Configurable Parameters:
- V
REF
, Precision I
OUT
/V
OUT
Set Point (DAC)
- Input Undervoltage Lockout (UVLO)
- Input Overvoltage Lockout (OVLO)
- Detection and protection
- Primary current leading edge blanking (0,
50 ns, 100 ns and 200 ns)
- Gate drive dead time (16 ns to 256 ns)
- Fixed switching frequency range: 31.25 kHz
to 2.0 MHz
- Slope compensation
- Quasi-resonant configuration with built-in
comparator and programmable offset voltage
adjustment
- Primary current offset adjustment
- Configurable GPIO pin options
• Integrated Low-Side Differential Current Sense
Amplifier
• ±5% Current Regulation
• Thermal Shutdown
Microcontroller Features
• Precision 8 MHz Internal Oscillator Block:
- Factory-calibrated to ±1%, typical
• Interrupt-Capable
- Firmware
- Interrupt-on-change pins
• Only 35 Instructions to Learn
• 4096 Words On-Chip Program Memory
• High-Endurance Flash:
- 100,000 write Flash endurance
- Flash retention: >40 years
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• Eight I/O Pins and One Input-Only Pin
- Two open-drain pins
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Five external channels
• Timer0: 8-bit Timer/Counter with 8-bit Prescaler
• Enhanced Timer1:
- 16-bit timer with prescaler
- Two selectable clock sources
• Timer2: 8-Bit Timer with Prescaler
- 8-bit period register
• I
2
C
TM
Communication:
- 7-bit address masking
- Two dedicated address registers
2014-2015 Microchip Technology Inc.
DS20005281B-page 1
MCP19114/5
Pin Diagram – 24-Pin QFN (MCP19114)
GPB1/AN4/VREF2
I
COMP
24
23
22
21
20
GPA0/AN0/TEST_OUT 1
19
18
V
DD
V
IN
I
FB
V
S
V
DR
PDRV
GPA1/AN1/CLKPIN
2
17
GPA2/AN2/T0CKI/INT
3
MCP19114
16
SDRV
GPA3/AN3
4
15
P
GND
GPA7/SCL/ICSPCLK
5
EXP-25
14
A
GND
I
P
GPA6/CCD/ICSPDAT
6
10
12
11
7
8
9
13
DESAT
N
GPB0/SDA
DESAT
P
/I
SOUT
GPA5/MCLR/TEST_EN
I
SP
DS20005281B-page 2
2014-2015 Microchip Technology Inc.
I
SN
MCP19114/5
TABLE 1:
I/O
24-PIN SUMMARY
24-Pin QFN
Interrupt
Pull-Up
ANSEL
Timers
MSSP
A/D
Basic
Additional
GPA0
GPA1
GPA2
GPA3
GPA5
GPA6
GPA7
GPB0
GPB1
DESAT
N
DESAT
P
/
I
SOUT
I
SP
I
SN
I
P
A
GND
P
GND
SDRV
PDRV
V
DR
V
DD
V
IN
V
S
I
FB
I
COMP
Note 1:
2:
3:
4:
5:
6:
1
2
3
4
7
6
5
8
24
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Y
Y
Y
Y
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
AN0
AN1
AN2
AN3
—
—
—
—
AN4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
INT
IOC
IOC
(4)
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
Y
(5)
Y
N
N
Y
—
—
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCLR
ICSPDAT
ICSPCLK
—
—
—
—
—
—
—
A
GND
P
GND
—
—
V
DR
V
DD
V
IN
—
—
—
Analog/Digital Debug Output
(1)
Sync Signal In/Out
(2)
—
—
Test Enable Input
Dual Capture/Compare Input
—
—
V
REF2(3)
DESAT Negative Input
DESAT
P
Input or I
SOUT
Output
(6)
Current Sense Amplifier Positive
Input
Current Sense Amplifier
Negative Input
Primary Input Current Sense
Small Signal Ground
Large Signal Ground
Secondary LS Gate Drive
Output
Primary LS Gate Drive
Output
Gate Drive Supply Voltage
V
DD
Output
Input Supply Voltage
Output Voltage Sense
Error Amplifier Feedback Input
Error Amplifier Output
The Analog/Digital Debug Output is selected through the control of the ABECON register.
Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the
MODECON register.
V
REF2
output selected when configured as master by proper configuration of the MSC<1:0> bits in the
MODECON register.
The IOC is disabled when MCLR is enabled.
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
When RFB of MODECON<5> =
0,
the internal feedback resistor and DESAT
P
input are enabled. When
RFB =
1,
I
SOUT
is enabled.
2014-2015 Microchip Technology Inc.
DS20005281B-page 3
MCP19114/5
Pin Diagram – 28-Pin QFN (MCP19115)
GPB5/AN6/ICSPCLK
GPB1/AN4/VREF2
GPB6/AN7
I
COMP
28
27
26
25
24
23
GPA0/AN0/TEST_OUT 1
GPA1/AN1/CLKPIN
GPA2/AN2/T0CKI/INT
GPB4/AN5/ICSPDAT
2
3
4
MCP19115
22
21
20
19
18
17
16
V
IN
I
FB
V
S
V
DD
V
DR
PDRV
SDRV
P
GND
A
GND
I
P
GPA3/AN3 5
GPA7/SCL
6
EXP-29
GPB0/SDA 10
DESAT
P
/I
SOUT
12
I
SP
13
DESAT
N
11
14
I
SN
GPA6/CCD
7
8
GPA5/MCLR/TEST_EN
9
15
GPB7/CCD
DS20005281B-page 4
2014-2015 Microchip Technology Inc.
MCP19114/5
TABLE 2:
I/O
28-PIN SUMMARY
28-Pin QFN
Interrupt
Pull-Up
ANSEL
Timers
MSSP
A/D
Basic
Additional
GPA0
GPA1
GPA2
GPA3
GPA5
GPA6
GPA7
GPB0
GPB1
GPB4
GPB5
GPB6
GPB7
DESAT
P
/
I
SOUT
DESAT
N
I
SP
I
SN
I
P
A
GND
P
GND
SDRV
PDRV
V
DR
V
DD
V
IN
V
S
I
FB
I
COMP
Note 1:
2:
3:
4:
5:
6:
1
2
3
5
8
7
6
10
26
4
27
28
9
12
11
13
14
15
16
17
18
19
20
21
22
23
24
25
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
AN0
AN1
AN2
AN3
—
—
—
—
AN4
AN5
AN6
AN7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
INT
IOC
IOC
(4)
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
Y
(5)
Y
N
N
Y
Y
Y
Y
Y
—
—
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCLR
—
—
—
—
ICSPDAT
ICSPCLK
—
—
—
—
—
—
—
A
GND
P
GND
—
—
V
DR
V
DD
V
IN
—
—
—
Analog/Digital Debug Output
(1)
Sync Signal In/Out
(2)
—
—
Test Enable Input
Dual Capture/Single
Compare1 Input
—
—
V
REF2(3)
—
—
—
Single Compare2 Input
DESAT
P
input or I
SOUT
Output
(6)
DESAT Negative Input
Current Sense Amplifier
Noninverting Input
Current Sense Amplifier
Inverting Input
Primary Input Current Sense
Small Signal Ground
Large Signal Ground
Secondary LS Gate Drive
Output
Primary LS Gate Drive Output
Gate Drive Supply Voltage
V
DD
Output
Input Supply Voltage
Output Voltage Sense
Error Amplifier Feedback input
Error Amplifier Output
The Analog/Digital Debug Output is selected through the control of the ABECON register.
Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the
MODECON register.
VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the
MODECON register.
The IOC is disabled when MCLR is enabled.
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
When RFB of MODECON<6> =
0,
the internal feedback resistor is enabled allow with DESAT
P
input.
When RFB =
1,
I
SOUT
is enabled.
2014-2015 Microchip Technology Inc.
DS20005281B-page 5
