MCP2050
LIN Transceiver with Voltage Regulator
Features
• The MCP2050 is compliant with:
- LIN Bus Specifications Version 1.3, and 2.x
- SAE J2602-2
• Support Baud Rates Up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage of 30V
• Wide LIN Compliant Supply Voltage, 6.0-18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC
®
EUSART and Standard USARTs
• Wake-up on LIN Bus Activity or Local Wake Input
• LIN Bus Pin
- Internal Pull-up Termination Resistor and
Diode for Slave Node
- Protected Against V
BAT
Shorts
- Protected Against Loss of Ground
- High Current Drive
• TXD and LIN Bus Dominant Time-out Function
• Two Low-power Modes
- TRANSMITTER OFF Mode: 90 µA (typical)
- POWER DOWN Mode: 4.5 µA (typical)
• Output Indicating Internal RESET State (POR or
SLEEP Wake)
• MCP2050 On-chip Voltage Regulator
- Output Voltage of 5.0V or 3.3V 70 mA
Capability with Tolerances of ±3% Over
Temperature Range
- Internal Short Circuit Current Limit
- Only External Filter and Load Capacitors
Needed
• Programmable Windowed Watchdog Timer
(WWDT)
- External Resistor Programmable from 7 ms
to 140 ms
- Disabled by Connecting the WWDTSELECT
Pin to V
REG
or Let the Pin Float
• Ratiometric Output of V
BAT
Voltage Scaled to
V
REG
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low Elec-
tromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB Pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design Requirements
Including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive
Applications”, Version 1.2, March 2011
• Multiple Package Options Including Small 5x5
QFN
Description
The MCP2050 provides a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602. The device
incorporates a voltage regulator with 5V or 3.3V 70 mA
regulated power supply output. The on-chip WWDT
allows users to adjust the size of the reset window by
using an external resistor. The ratiometric VBAT pin
scales down V
BAT
to the range of V
REG
so it can be
monitored by an A/D converter.
The device has been designed to meet the stringent
quiescent current requirements of the automotive
industry and will survive +43V load dump transients,
and double battery jumps.
MCP2050 family members:
- MCP2050-500, 14-pin, LIN driver with 5.0V
regulator
- MCP2050-330, 14-pin, LIN driver with 3.3V
regulator
- MCP2050-500, 20-pin QFN, LIN driver with
5.0V regulator
- MCP2050-330, 20-pin QFN, LIN driver with
3.3V regulator
2012 Microchip Technology Inc.
DS22299B-page 1
MCP2050
Package Types (Top View)
MCP2050
PDIP, SOIC
MCP2050
QFN
WWDTRESET
17
V
BAT
RATIO
18
NC
NC
V
BAT
RATIO
R
XD
CS/LWAKE
V
REG
T
XD
RESET
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
WWDTRESET
WWDTTRIG
WWDTSELECT
FAULT/TXE
V
BB
L
BUS
V
SS
20
19
16
NC
L
BUS
V
SS
NC
NC
Block Diagram
4.2V
NC
10
6
7
8
9
MCP2050
R
XD
CS/LWAKE
V
REG
T
XD
RESET
1
2
3
4
5
15
14
MCP205
13
12
11
WWDTTRIG
WWDTSELECT
FAULT/TXE
V
BB
NC
WWDTTRIG
WWDTselect
Programmable
Windowed Watchdog
V
REG
WWDTRESET
Short Circuit
Protection
Thermal
Protection
Voltage
Regulator
RESET
V
BB
Ratiometric
Reference
Bus Wakeup
V
REG
Internal Circuits 4.2V
V
REG
Wake-Up
Logic and
Power Control
RXD
CS/LWAKE
TXD
FAULT/TXE
V
BB
Thermal
and
Short Circuit
Protection
V
REG
V
BAT
RATIO
300
Bus
Dominant
Timer
Slope Control
~30
k
L
BUS
V
SS
DS22299B-page 2
2012 Microchip Technology Inc.
MCP2050
1.0
FUNCTION DESCRIPTION
1.1
Modes of Operation
The MCP2050 provides a physical interface between a
microcontroller and a LIN half-duplex bus. It is intended
for automotive and industrial applications with serial
bus baud rates up to 20 kbaud. This device will trans-
late the CMOS/TTL logic levels to LIN logic levels, and
vice versa. The device offers optimum EMI and ESD
performance; it can withstand high voltage on the LIN
bus. The device supports two low-power modes to
meet automotive industry power consumption require-
ments. The MCP2050 also provides a +5V or 3.3V
70 mA regulated power output.
The MCP2050 works in five modes: POWER-ON-
RESET mode, POWER-DOWN mode, READY mode,
OPERATION mode, and TRANSMITTER OFF mode.
For an overview of all operational modes, please refer
to
Table 1-1.
For the operational mode transition,
please refer to
Figure 1-1.
FIGURE 1-1:
STATE DIAGRAM
CS/LWAKE=0 or FAULT/TXE=0 or TXD=0
POR
(2)
VREG OFF
RX OFF
TX OFF
VBB>V
ON
READY
VREG ON
RX ON
TX OFF
CS/LWAKE=1&
FAULT/TXE=0&
VREG_OK=1
(1)
CS/LWAKE=1 &
FAULT/TXE=1
(3)
&
TXD=1&
VREG_OK=1
(1)
CS/LWAKE=1 OR
Voltage Rising Edge on LBUS
TX OFF
VREG ON
RX ON
TX OFF
CS/LWAKE=0
CS/LWAKE=1&
FAULT/TXE=1
(3)
&
TXD=1
OPERATION
VREG ON
RX ON
TX ON
CS/LWAKE=1&
FAULT/TXE=0
POWER-DOWN
VREG OFF
RX OFF
TX OFF
CS/LWAKE=0
Note 1:
VREG_OK: Regulator Output Voltage > 0.8V
REG_NOM.
2:
If the voltage on pin VBB falls below V
OFF
, the device will enter POWER ON RESET mode from all other
modes, which is not shown in the figure.
3:
FAULT/TXE = 1 represents input High and no fault conditions. FAULT/TXE = 0 represents input Low or a
fault condition. Refer to
Table 1-3.
1.1.1
POWER-ON-RESET MODE
Upon application of V
BB
, or whenever the voltage on
VBB is below the threshold of regulator turn off voltage
V
OFF
(typically. 4.50V), the device enters POWER-ON-
RESET mode (POR). During this mode, the device
maintains the digital section in a reset mode and waits
until the voltage on pin VBB rises above the threshold
of regulator turn on voltage V
ON
(typically 5.75V) to
enter into READY mode. In POWER-ON-RESET
mode, the LIN physical layer and voltage regulator are
disabled, and RESET output is forced to LOW.
2012 Microchip Technology Inc.
DS22299B-page 3
MCP2050
1.1.2
READY MODE
The device enters READY mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn on voltage V
ON
or from POWER-DOWN
mode when a remote or local wake-up event happens.
Upon entering READY mode, the voltage regulator and
receiver section of the transceiver are powered up. The
transmitter remains in off state. The device is ready to
receive data but not to transmit. In order to minimize the
power consumption, the regulator operates in a
reduced power mode. It has a lower GBW product and
thus is slower. However, the 70 mA drive capability is
unchanged.
The device stays in READY mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is HIGH (‘1’).
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, by removing the
internal fault condition and the CPU returning the
FAULT/TXE high. The transmitter will not be enabled
even if the FAULT/TXE pin is brought high externally,
when the internal fault is still present. However,
externally forcing the FAULT/TXE high, while the
internal fault is still present, should be avoided since
this will induce high current and power dissipation in
the FAULT/TXE pin.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.1.5
POWER-DOWN MODE
1.1.3
OPERATION MODE
If V
REG
is OK
(V
REG
> 0.8 V
REG
_
NOM
),
CS/LWAKE pin,
FAULT/TXE pin and TXD pin are HIGH, the part enters
the OPERATION mode from either READY or
TRANSMITTER OFF mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between L
BUS
and V
BB
is
connected only in this mode.
The device goes into the POWER-DOWN mode at the
falling edge on CS/LWAKE; or to the TRANSMITTER
OFF mode at the falling on FAULT/TXE while CS/
LWAKE stays HIGH.
In POWER-DOWN mode, the transceiver and the
voltage regulator are both off. Only the Bus Wake-up
section and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest power mode.
If any bus activity (e.g. a BREAK character) occurs
during POWER-DOWN mode, the device will
immediately enter READY mode and enable the volt-
age regulator. Then, once the regulator output has sta-
bilized (approximately 0.3 ms to 1.2 ms) it goes to
OPERATION mode. Refer to
Section
1.1.6 “Remote
Wake-up”
for more details.
The part will also enter READY mode from POWER-
DOWN mode, followed by OPERATION mode, if the
CS/LWAKE pin becomes active HIGH (‘1’).
1.1.4
TRANSMITTER OFF MODE
1.1.6
REMOTE WAKE-UP
In TRANSMITTER OFF mode, the receiver is enabled
but the L
BUS
transmitter is off. It is a lower power mode.
In order to minimize the power consumption, the
window watchdog timer is disabled and the regulator
operates in a reduced power mode. It has a lower GBW
product and thus is slower. However, the 70 mA drive
capability is unchanged.
The remote wake-up sub module observes the L
BUS
in
order to detect bus activity. In POWER DOWN mode,
normal LIN recessive/dominant threshold is disabled,
and the LIN bus Wake-Up Voltage Threshold
V
WK(LBUS)
is used to detect bus activities. Bus activity
is detected when the voltage on the L
BUS
falls below
the LIN bus Wake-Up Voltage Threshold V
WK(LBUS)
(approximately 3.4V) for at least t
BDB
(a typical duration
of 80 µs) followed by a rising edge. Such a condition
causes the device to leave POWER-DOWN mode.
TABLE 1-1:
State
POR
READY
OPERATION
OVERVIEW OF OPERATIONAL MODES
Transmitter Receiver
OFF
OFF
ON
OFF
ON
ON
Internal
Voltage Watch Dog
Wake Module Regulator
Timer
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
ON
Operation
Transfer to READY mode after V
BB
>V
ON
.
If CS/LWAKE high, then proceed to
OPERATION or TRANSMITTER OFF mode.
If CS/LWAKE low level, then Power down.
If FAULT/TXE low level, then
TRANSMITTER-OFF mode.
On LIN bus rising edge or CS/LWAKE high
level, go to READY mode.
If CS/LWAKE low level, then Power down.
If FAULT/TXE high, then OPERATION mode.
Bus Off state
Normal
Operation
mode
Lowest Power
mode
Bus Off state,
Lower Power
mode
Comments
POWER DOWN
TRANSMITTER
OFF
OFF
OFF
OFF
ON
ON
Activity Detect
OFF
OFF
ON
OFF
OFF
2012 Microchip Technology Inc.
DS22299B-page 4
MCP2050
1.2
WINDOWED WATCHDOG RESET
The Watchdog Timer monitors for activity on the
Windowed Watchdog Timer Trigger input pin
WWDTTRIG. The WWDTTRIG pin is expected to be
strobed within a given time frame. When this time
frame has expired, without an edge transition on the
WWDTTRIG pin, the WWDTRESET pin is driven active
(LOW) to reset the system. This feature is enabled by
connecting a resistor between the WWDTSELECT pin
and V
SS
. Monitoring is then done by requiring the host
processor to force an falling edge transition on the
WWDTTRIG pin within a predetermined time frame
(T
WD
).
The start time of the trigger window is fixed at 50% of
the total watchdog period, after the last trigger. The
length of the window is determined by the value of the
resistor on pin WWDTSELECT. The Watchdog Timer is
disabled if WWDTSELECT is floating.
1.2.1
WWDT During Initial Power-up
The WWDTRESET is driven high after a power-on
reset. The Watchdog Timer begins counting at this
point, awaiting an edge on WWDTTRIG pin. Note that
there is no window enabled, yet. If no falling edge is
detected on the WWDTTRIG pin before the timer
expires, the WWDTRESET is pulse low and the timer
is restarted. When a trigger edge on the WWDTTRIG
pin is seen, the window is enabled and the timer is reset.
FIGURE 1-2:
Internal
reset
WWDTRESET DURING INITIAL POWER-UP
WW
DTRESET
t
POWERUP
t
WDRST
t
POWERUP
t
WDRST
t
POWERUP
FIGURE 1-2: “WWDTRESET DURING INITIAL
POWER-UP”
shows the behavior of the WWDTRE-
SET pin after a system reset with no trig at all. If no trig
is given during the power-up window, WWDTRESET is
reset low for the time t
WDRST
.
The power-up window length t
POWERUP
duration is
determined by the value of the resistor connected
between pin WWDTSELECT and pin VSS, while the
reset pulse duration is about 150 us.
Duration for t
POWERUP
and t
WDRST
are:
t
POWERUP
= 0.8 ms x (R
WWDTSELECT
+1) +/- 15%
t
WDRST
= 150us +/- 35%
R
WWDTSELECT
is in k
Once a trig is asserted, the power-up sequence “stops”
and the normal behavior begins.
detected before the trigger window (too early trig-
ger); WWDTRESET is asserted (LOW) immedi-
ately after the falling edge is detected for
approximately t
WDRST
; the counter is reset and the
next watchdog period begins at the rising edge of
the voltage on WWDTRESET pin (Figure
1-14).
• No pulse on the WWDTTRIG pin is detected dur-
ing the whole watchdog window (no trigger),
WWDTRESET is asserted (LOW) for approxi-
mately t
WDRST
when the timer has expired; the
counter is reset and the next watchdog period
begins at the rising edge of the voltage on
WWDTRESET pin (Figure
1-5).
The trigger window is between 50% to 100% of the
watchdog window length. The window length is
determined by the external resistor between
WWDTSELECT pin and VSS.
WINDOW LENGTH = 0.2 ms x (RWWDTSELECT + 1)+/
-15%.
t
WDRST
= 150uS+/-35%
R
WWDTSELECT
is in k; its value ranges from 33 k to
680 k and window length ranges from 6.8 ms to 136+/
-15%.
If the WWDTSELECT pin is floating, the watchdog is
disabled and the WWDTRESET remains HIGH.
1.2.2
WINDOWED WATCHDOG
BEHAVIOR
After windowed watchdog begins its normal behavior,
three different cases can appear.
• A pulse (falling edge) on the WWDTTRIG pin is
detected within the trigger window; the watchdog
timer will be reset, and a new watchdog period will
begin; WWDTRESET pin remains high (Figure
1-3.)
• A pulse (falling edge) on the WWDTTRIG pin is
2012 Microchip Technology Inc.
DS22299B-page 5
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