MCP39F511
Power-Monitoring IC with Calculation and Energy Accumulation
Features
• Power Monitoring Accuracy Capable of 0.1%
Error Across 4000:1 Dynamic Range
• Built-In Calculations on Fast 16-Bit Processing
Core
- Active, Reactive, Apparent Power
- True RMS Current, RMS Voltage
- Line Frequency, Power Factor
• 64-bit Wide Import and Export Active Energy
Accumulation Registers
• 64-bit Four Quadrant Reactive Energy
Accumulation Registers
• Signed Active and Reactive Power Outputs
• Dedicated Zero Crossing Detection (ZCD) Pin
Output with Less than 200 µs Latency
• Dedicated PWM Output Pin with Programmable
Frequency and Duty Cycle
• Automatic Event Pin Control through Fast Voltage
Surge Detection Less than 5 ms Delay
• Two Wire Serial Protocol with Selectable Baud
Rate Up to 115.2 kbps using Universal
Asynchronous Receiver/Transmitter (UART)
• Four Independent Registers for Minimum and
Maximum Output Quantity Tracking
• Fast Calibration Routines and Simplified
Command Protocol
• 512 Bytes User-Accessible EEPROM through
Page Read/Write Commands
• Low-Drift Internal Voltage Reference, 10 ppm/°C
Typical
• 28-lead 5x5 QFN Package
• Extended Temperature Range -40°C to +125°C
Description
The MCP39F511 is a highly integrated, complete
single-phase power-monitoring IC designed for
real-time measurement of input power for
AC/DC power supplies, power distribution units,
consumer and industrial applications. It includes
dual-channel Delta-Sigma ADCs, a 16-bit calculation
engine, EEPROM and a flexible 2-wire interface. An
integrated low-drift voltage reference with 10 ppm/°C in
addition to 94.5 dB of SINAD performance on each
measurement channel allows for better than 0.1%
accurate designs across a 4000:1 dynamic range.
Package Types
MCP39F511
5x5 QFN*
REFIN+/OUT
COMMON
B
MCLR
D
GND
DV
DD
D
GND
DR
28 27 26 25 24 23 22
EVENT1 1
NC 2
NC 3
UART_RX 4
COMMON
A
5
OSCI 6
OSCO 7
8
NC
9 10 11 12 13 14
UART_TX
RESET
AV
DD
PWM
NC
EP
29
21 A
GND
20 AN_IN
19 V1+
18 V1-
17 I1-
16 I1+
15 EVENT2
Applications
• Power Monitoring for Home Automation
• Industrial Lighting Power Monitoring
• Real-Time Measurement of Input Power for
AC/DC Supplies
• Intelligent Power Distribution Units
*Includes Exposed Thermal Pad (EP);
see
Table 3-1.
2015 Microchip Technology Inc.
DS20005393B-page 1
ZCD
MCP39F511
Functional Block Diagram
OSCI
OSCO
Timing
Generation
Internal
Oscillator
SINC
3
Digital Filter
UART
Serial
Interface
16-BIT
CORE
FLASH
UART_TX
UART_RX
AV
DD
A
GND
DV
DD
D
GND
I1+
I1-
+
PGA
-
24-bit Delta-Sigma
Multi-level
Modulator ADC
PWM
V1+
V1-
+
PGA
-
24-bit Delta-Sigma
Multi-level
Modulator ADC
SINC
3
Digital Filter
EVENT1
Calculation
Engine
(CE)
EVENT2
Digital Outputs
ZCD
AN_IN
10-bit SAR
ADC
DS20005393B-page 2
2015 Microchip Technology Inc.
MCP39F511
MCP39F511 Typical Application – Single Phase, Two-Wire Application Schematic
10
LOAD
+3.3V
0.1 µF
1 µF
0.1 µF
1 k
+
2 m
-
1 k
I1-
33 nF
1 k
V1-
33 nF
499 k 499 k
V1+
1 k
33 nF
I1+
33 nF
AV
DD
DV
DD
RESET
REFIN/OUT+
0.1 µF
UART_TX
to MCU UART
UART_RX
to MCU UART
MCP39F511
(OPTIONAL)
N.C.
Leave Floating
Connect on PCB
+3.3V
MCP9700A
NC
NC
NC
NC
DR
COMMON
A,B
AN_IN
EVENT1
EVENT2
ZCD
PWM
OSCO
4 MHz
OSCI
22 pF
22 pF
D
GND
A
GND
(OPTIONAL)
0.47 µ F 470
MCP1754
+3.3V
0.01 µF
N
L
D
GND
470 µF
A
GND
Note 1:
The MCP39F511 demonstration board uses a switching power supply, however a low-cost
capacitive-based supply, as shown here, is sufficient for many applications.
2:
The external sensing components shown here, a 2 mΩ shunt, two 499 kΩ and 1 kΩ resistors for the
1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers
defined in
Section 6.0 “Register Descriptions”.
By choosing low-tolerance components of these
values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero
calibration. See
Section 9.0 “MCP39F511 Calibration”
for more information.
2015 Microchip Technology Inc.
DS20005393B-page 3
MCP39F511
1.0
ELECTRICAL
CHARACTERISTICS
† Notice:
Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Absolute Maximum Ratings †
DV
DD
.................................................................. -0.3 to +4.5V
AV
DD
.................................................................. -0.3 to +4.0V
Digital inputs and outputs w.r.t. A
GND
............... -0.3V to +4.0V
Analog Inputs (I+,I-,V+,V-) w.r.t. A
GND
............... ....-2V to +2V
V
REF
input w.r.t. A
GND
........................ ....-0.6V to AV
DD
+0.6V
Maximum Current out of D
GND
pin..............................300 mA
Maximum Current into DV
DD
pin .................................250 mA
Maximum Output Current Sunk by Digital IO ................25 mA
Maximum Current Sourced by Digital IO.......................25 mA
Storage temperature .....................................-65°C to +150°C
Ambient temperature with power applied......-40°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V
ESD on all other pins (HBM,MM) ........................4.0 kV, 200V
1.1
Specifications
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD,
DV
DD
= +2.7 to +3.6V, T
A
= -40°C to +125°C,
MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Power Measurement
Active Power
(Note
1)
Sym.
P
Min.
—
Typ.
±0.1
Max.
—
Units
%
Test Conditions
4000:1 Dynamic Range
on Current Channel
(Note
2)
4000:1 Dynamic Range
on Current Channel
(Note
2)
4000:1 Dynamic Range
on Current Channel
(Note
2)
4000:1 Dynamic Range
on Current Channel
(Note
2)
4000:1 Dynamic Range
on Voltage Channel
(Note
2)
Reactive Power
(Note
1)
Q
—
±0.1
—
%
Apparent Power
(Note
1)
S
—
±0.1
—
%
Current RMS
(Note
1)
I
RMS
—
±0.1
—
%
Voltage RMS
(Note
1)
V
RMS
—
±0.1
—
%
Power Factor
(Note
1)
Line Frequency
(Note
1)
Note 1:
2:
LF
—
—
±0.1
±0.1
—
—
%
%
Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4
line cycles.
Specification by design and characterization; not production tested.
N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or T
CAL
= 80 ms for
50 Hz line.
Applies to Voltage Sag and Voltage Surge events only.
Applies to all gains. Offset and gain errors depend on the PGA gain setting. See
Section 2.0 “Typical Performance
Curves”
for typical performance.
V
IN
= 1V
PP
= 353 mV
RMS
@ 50/60 Hz.
Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the
performance listed in the respective specification.
3:
4:
5:
6:
7:
8:
Lower baud rates selectable only on system versions 0xFA14 and later.
DS20005393B-page 4
2015 Microchip Technology Inc.
MCP39F511
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD,
DV
DD
= +2.7 to +3.6V, T
A
= -40°C to +125°C,
MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Auto-Calibration Time
Minimum Time
for Voltage Surge/Sag
Detection
Analog Input
Absolute Voltage
Analog Input
Leakage Current
Differential Input
Voltage Range
Offset Error
Offset Error Drift
Gain Error
Gain Error Drift
Differential Input
Impedance
Sym.
t
CAL
t
AC_SASU
Min.
—
—
Typ.
2
N
x (1/f
LINE
)
Max.
—
—
Units
ms
ms
Test Conditions
Note 3
Note 4
Calibration, Calculation and Event Detection Times
see
Section 7.0
24-Bit Delta-Sigma ADC Performance
V
IN
A
IN
(I1+ – I1-),
(V1+ – V1-)
V
OS
GE
Z
IN
-1
—
-600/GAIN
-1
—
-4
—
232
142
72
38
36
33
Signal-to-Noise
and Distortion Ratio
Total Harmonic Distortion
Signal-to-Noise Ratio
Spurious Free
Dynamic Range
Crosstalk
AC Power
Supply Rejection Ratio
DC Power
Supply Rejection Ratio
Note 1:
2:
—
1
—
—
0.5
—
1
—
—
—
—
—
—
94.5
-106.5
95
111
-122
-73
+1
—
+600/GAIN
+1
—
+4
—
—
—
—
—
—
—
—
-103
—
—
—
—
V
nA
mV
mV
µV/°C
%
ppm/°C
k
k
k
k
k
k
dB
dBc
dB
dB
dB
dB
AV
DD
and
DV
DD
= 3.3V + 0.6V
PP
,
100 Hz, 120 Hz, 1 kHz
AV
DD
and DV
DD
= 3.0 to
3.6V
G=1
G=2
G=4
G=8
G = 16
G = 32
Note 6
Note 6
Note 6
Note 6
Note 5
V
REF
= 1.2V,
proportional to V
REF
SINAD
THD
SNR
SFDR
CTALK
AC PSRR
92
—
92
—
—
—
DC PSRR
—
-73
—
dB
Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4
line cycles.
Specification by design and characterization; not production tested.
N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or T
CAL
= 80 ms for
50 Hz line.
Applies to Voltage Sag and Voltage Surge events only.
Applies to all gains. Offset and gain errors depend on the PGA gain setting. See
Section 2.0 “Typical Performance
Curves”
for typical performance.
V
IN
= 1V
PP
= 353 mV
RMS
@ 50/60 Hz.
Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the
performance listed in the respective specification.
3:
4:
5:
6:
7:
8:
Lower baud rates selectable only on system versions 0xFA14 and later.
2015 Microchip Technology Inc.
DS20005393B-page 5
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