MCP4728
12-Bit, Quad Digital-to-Analog Converter with EEPROM Memory
Features
• 12-Bit Voltage Output DAC with Four Buffered
Outputs
• On-Board Nonvolatile Memory (EEPROM) for
DAC Codes and I
2
C™ Address Bits
• Internal or External Voltage Reference Selection
• Output Voltage Range:
- Using Internal V
REF
(2.048V):
0.000V to 2.048V with Gain Setting = 1
0.000V to 4.096V with Gain Setting = 2
- Using External V
REF
(V
DD
):
0.000V to V
DD
• ±0.2 Least Significant Bit (LSB) Differential
Nonlinearity (DNL) (typical)
• Fast Settling Time: 6 µs (typical)
• Normal or Power-Down Mode
• Low Power Consumption
• Single-Supply Operation: 2.7V to 5.5V
• I
2
C Interface:
- Address bits: User Programmable to
EEPROM
- Standard (100 kbps), Fast (400 kbps) and
High Speed (HS) Mode (3.4 Mbps)
• 10-Lead MSOP Package
• Extended Temperature Range: -40°C to +125°C
Description
The MCP4728 device is a quad, 12-bit voltage output
Digital-to-Analog Convertor (DAC) with nonvolatile
memory (EEPROM). Its on-board precision output
amplifier allows it to achieve rail-to-rail analog output
swing.
The DAC input codes, device configuration bits, and
I
2
C address bits are programmable to the nonvolatile
memory (EEPROM) by using I
2
C serial interface
commands. The nonvolatile memory feature enables
the DAC device to hold the DAC input codes during
power-off time, allowing the DAC outputs to be
available immediately after power-up with the saved
settings. This feature is very useful when the DAC
device is used as a supporting device for other devices
in the application’s network.
The MCP4728 device has a high precision internal
voltage reference (V
REF
= 2.048V). The user can select
the internal reference or external reference (V
DD
) for
each channel individually.
Each channel can be operated in Normal mode or
Power-Down mode individually by setting the
configuration register bits. In Power-Down mode, most
of the internal circuits in the powered down channel are
turned off for power savings, and the output amplifier
can be configured to present a known low, medium, or
high resistance output load.
The MCP4728 device includes a Power-on Reset
(POR) circuit to ensure reliable power-up and an
on-board charge pump for the EEPROM programming
voltage.
The MCP4728 has a two-wire I
2
C compatible serial
interface for standard (100 kHz), fast (400 kHz), or high
speed (3.4 MHz) mode.
The MCP4728 DAC is an ideal device for applications
requiring design simplicity with high precision, and for
applications requiring the DAC device settings to be
saved during power-off time.
The MCP4728 device is available in a 10-lead MSOP
package and operates from a single 2.7V to 5.5V
supply voltage.
Applications
•
•
•
•
•
•
•
•
•
Set Point or Offset Adjustment
Sensor Calibration
Closed-Loop Servo Control
Low Power Portable Instrumentation
PC Peripherals
Programmable Voltage and Current Source
Industrial Process Control
Instrumentation
Bias Voltage Adjustment for Power Amplifiers
©
2010 Microchip Technology Inc.
DS22187E-page 1
MCP4728
Package Type
MCP4728
MSOP
V
DD
1
SCL 2
SDA 3
LDAC 4
RDY/BSY 5
10 V
SS
9 V
OUT
D
8 V
OUT
C
7 V
OUT
B
6 V
OUT
A
Functional Block Diagram
LDAC
EEPROM A
V
DD
V
SS
INPUT
REGISTER A
EEPROM B
Output
Logic
OP
AMP A
Power Down
Control
Output
Logic
OP
AMP B
Power Down
Control
OP
AMP C
Power Down
Control
OP
AMP D
Power Down
Control
Output
Logic
V
OUT
D
Output
Logic
V
OUT
C
V
OUT
B
V
OUT
A
UDAC
OUTPUT
REGISTER A
UDAC
OUTPUT
REGISTER B
UDAC
OUTPUT
REGISTER C
UDAC
V
REF
A
Gain
Control
STRING DAC A
V
REF
B
Gain
Control
I
2
C Interface Logic
INPUT
REGISTER B
EEPROM C
STRING DAC B
V
REF
C
SDA
SCL
Gain
Control
INPUT
REGISTER C
EEPROM D
STRING DAC C
V
REF
D
Gain
Control
RDY/BSY
INPUT
REGISTER D
Internal V
REF
(2.048V)
V
DD
OUTPUT
REGISTER D
V
REF
Selector
STRING DAC D
V
REF
(V
REF
A, V
REF
B, V
REF
C, V
REF
D)
DS22187E-page 2
©
2010 Microchip Technology Inc.
MCP4728
1.0
ELECTRICAL
CHARACTERISTICS
†
Notice:
Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings†
V
DD
...................................................................................6.5V
All inputs and outputs w.r.t V
SS
................. -0.3V to V
DD
+0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins ............................................. ±110 mA
Current at Output Pins ...............................................±25 mA
Storage Temperature ...................................-65°C to +150°C
Ambient Temp. with Power Applied .............-55°C to +125°C
ESD protection on all pins
................ ≥
4 kV HBM,
≥
400V MM
Maximum Junction Temperature (T
J
) ......................... +150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, all parameters apply at V
DD
= +2.7V to 5.5V, V
SS
= 0V,
R
L
= 5 kΩ, C
L
= 100 pF, G
X
= 1, T
A
= -40°C to +125°C. Typical values are at +25°C, V
IH
= V
DD
, V
IL
= V
SS.
Parameter
Power Requirements
Operating Voltage
Supply Current with
External Reference
(V
REF
= V
DD
)
(Note
1)
V
DD
I
DD_EXT
2.7
—
—
—
—
Power-Down Current with
External Reference
Supply Current with
Internal Reference
(V
REF
= Internal)
(Note
1)
I
PD_EXT
I
DD_INT
—
—
800
600
400
200
40
800
5.5
1400
—
—
—
—
1400
V
µA
µA
µA
µA
nA
µA
V
REF
= V
DD
, V
DD
= 5.5V
All 4 channels are in Normal mode.
3 channels are in Normal mode,
1 channel is powered down.
2 channels are in Normal mode,
2 channel are powered down.
1 channel is in Normal mode,
3 channels are powered down.
All 4 channels are powered down.
(V
REF
= V
DD
)
V
REF
= Internal Reference
V
DD
= 5.5V
All 4 channels are in normal mode.
3 channels are in Normal mode,
1 channel is powered down.
2 channels are in Normal mode,
2 channels are powered down.
1 channel is in Normal mode,
3 channels are powered down.
All 4 channels are powered down.
V
REF
= Internal Reference
Symbol
Min
Typical
Max
Units
Conditions
—
—
—
600
400
200
45
—
—
—
60
µA
µA
µA
µA
Power-Down Current with
Internal Reference
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
I
PD_INT
—
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
The power-up ramp rate measures the rise of V
DD
over time.
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
Test code range: 100 - 4000 codes, V
REF
= V
DD
, V
DD
= 5.5V.
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
This parameter is indirectly tested by Offset and Gain error testing.
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
This time delay is measured from the falling edge of ACK pulse in I
2
C command to the beginning of V
OUT
.
This time delay is not included in the output settling time specification.
©
2010 Microchip Technology Inc.
DS22187E-page 3
MCP4728
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at V
DD
= +2.7V to 5.5V, V
SS
= 0V,
R
L
= 5 kΩ, C
L
= 100 pF, G
X
= 1, T
A
= -40°C to +125°C. Typical values are at +25°C, V
IH
= V
DD
, V
IL
= V
SS.
Parameter
Power-on Reset
Threshold Voltage
Power-Up Ramp Rate
DC Accuracy
Resolution
Integral Nonlinearity (INL)
Error
DNL Error
Offset Error
Offset Error Drift
Gain Error
n
INL
DNL
V
OS
ΔV
OS
/°C
G
E
12
—
-0.75
—
—
—
-1.25
—
±2
±0.2
5
±0.16
±0.44
0.4
—
±13
±0.75
20
—
—
+1.25
Bits
LSB
LSB
mV
Code Change: 000h to FFFh
Note 5
Note 5
Code = 000h
See
Figure 2-24
Symbol
V
POR
V
RAMP
Min
—
1
Typical
2.2
—
Max
—
—
Units
V
V/s
Conditions
All circuits, including EEPROM, are
ready to operate.
Note 2, Note 4
ppm/°C -45°C to +25°C
ppm/°C +25°C to +125°C
% of
FSR
Code = FFFh,
Offset error is not included.
Typical value is at room
temperature
See
Figure 2-25
Gain Error Drift
Internal Voltage Reference
Temperature Coefficient
ΔG
E
/°C
V
REF
ΔV
REF
/°C
—
2.007
—
—
—
—
-3
2.048
125
0.25
45
0.09
290
1.2
1.0
400
—
2.089
—
—
—
—
—
—
—
—
ppm/°C
V
ppm/°C -40 to 0°C
LSB/°C
ppm/°C 0 to +125°C
LSB/°C
µV
p-p
μV
H
Z
Hz
Code = FFFh,
0.1 – 10 Hz, G
x
= 1
Code = FFFh, 1 kHz, G
x
= 1
Code = FFFh, 10 kHz, G
x
= 1
Internal Voltage Reference (V
REF
), (Note
3)
Reference Output Noise
Output Noise Density
1/f Corner Frequency
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
E
NREF
e
NREF
f
CORNER
—
—
—
—
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
The power-up ramp rate measures the rise of V
DD
over time.
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
Test code range: 100 - 4000 codes, V
REF
= V
DD
, V
DD
= 5.5V.
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
This parameter is indirectly tested by Offset and Gain error testing.
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
This time delay is measured from the falling edge of ACK pulse in I
2
C command to the beginning of V
OUT
.
This time delay is not included in the output settling time specification.
DS22187E-page 4
©
2010 Microchip Technology Inc.
MCP4728
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at V
DD
= +2.7V to 5.5V, V
SS
= 0V,
R
L
= 5 kΩ, C
L
= 100 pF, G
X
= 1, T
A
= -40°C to +125°C. Typical values are at +25°C, V
IH
= V
DD
, V
IL
= V
SS.
Parameter
Output Voltage Swing
Full Scale Range
(Note
7)
Symbol
V
OUT
FSR
Min
—
—
—
—
Output Voltage
Settling Time
Analog Output Time Delay
from Power-Down Mode
Time delay to settle to new
reference
(Note
4, Note 6)
Power Supply Rejection
Capacitive Load Stability
Slew Rate
Phase Margin
Short Circuit Current
T
SETTLING
Td
ExPD
Td
REF
—
—
—
—
PSRR
C
L
SR
p
M
I
SC
—
—
—
—
—
Typical
FSR
V
DD
V
REF
2 * V
REF
6
4.5
26
44
-57
—
0.55
66
15
Max
—
—
—
—
—
—
—
—
—
1000
—
—
24
Units
V
V
V
V
µs
µs
µs
µs
dB
pF
V/µs
Note 7
V
REF
= V
DD
FSR = from 0.0V to V
DD
V
REF
= Internal, G
x
= 1,
FSR = from 0.0 V to V
REF
V
REF
= Internal, G
x
= 2,
FSR = from 0.0V to 2 * V
REF
Note 8
V
DD
= 5V,
Note 4, Note 9
From External to Internal
Reference
From Internal to External
Reference
V
DD
= 5V ±10%, V
REF
=
Internal
R
L
= 5 kΩ
No oscillation,
Note 4
Conditions
Analog Output (Output Amplifier)
Degree C
L
= 400 pF, R
L
=
∞
(°)
mA
V
DD
= 5V,
All V
OUT
Pins = Grounded.
Tested at room temperature.
Note 4
Normal mode
Power-Down mode 1
(PD1:PD0 = 0:1), V
OUT
to V
SS
Power-Down mode 2
(PD1:PD0 = 1:0), V
OUT
to V
SS
Power-Down mode 3
(PD1:PD0 = 1:1), V
OUT
to V
SS
Short Circuit Current
Duration
DC Output Impedance
(Note
4)
T
SC_DUR
R
OUT
—
—
—
—
—
Infinite
1
1
100
500
—
—
—
—
—
hours
Ω
kΩ
kΩ
kΩ
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
The power-up ramp rate measures the rise of V
DD
over time.
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
Test code range: 100 - 4000 codes, V
REF
= V
DD
, V
DD
= 5.5V.
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
This parameter is indirectly tested by Offset and Gain error testing.
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
This time delay is measured from the falling edge of ACK pulse in I
2
C command to the beginning of V
OUT
.
This time delay is not included in the output settling time specification.
©
2010 Microchip Technology Inc.
DS22187E-page 5
