MCP6S91/2/3
Single-Ended, Rail-to-Rail I/O, Low-Gain PGA
Features
• Multiplexed Inputs: 1 or 2 channels
• 8 Gain Selections:
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI
™
)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max.)
• Offset Mismatch Between Channels: 0 µV
• High Bandwidth: 1 to 18 MHz (typ.)
• Low Noise: 10 nV/√Hz @ 10 kHz (typ.)
• Low Supply Current: 1.0 mA (typ.)
• Single Supply: 2.5V to 5.5V
• Extended Temperature Range: -40°C to +125°C
Description
The Microchip Technology Inc. MCP6S91/2/3 are
analog Programmable Gain Amplifiers (PGAs). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to two chan-
nels through a SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high-speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single-
supply applications needing flexible performance or
multiple inputs.
The one-channel MCP6S91 and the two-channel
MCP6S92 are available in 8-pin PDIP, SOIC and MSOP
packages. The two-channel MCP6S93 is available in a
10-pin MSOP package. All parts are fully specified from
-40°C to +125°C.
Typical Applications
•
•
•
•
•
•
A/D Converter Driver
Multiplexed Analog Applications
Data Acquisition
Industrial Instrumentation
Test Equipment
Medical Instrumentation
Package Types
MCP6S91
PDIP, SOIC, MSOP
V
OUT
1
CH0 2
V
REF
3
V
SS
4
8 V
DD
7 SCK
6 SI
5 CS
MCP6S93
MSOP
V
OUT
1
CH0 2
CH1 3
V
REF
4
V
SS
5
10 V
DD
9 SCK
8 SO
7 SI
6 CS
Block Diagram
V
DD
CH0
CH1
CS
SI
SO
SCK
MUX
Resistor Ladder (R
LAD
)
MCP6S92
PDIP, SOIC, MSOP
V
OUT
V
OUT
1
CH0 2
CH1 3
V
SS
4
8 V
DD
7 SCK
6 SI
5 CS
SPI™
Logic
8
Gain
Switches
R
F
R
G
V
SS
V
REF
2004 Microchip Technology Inc.
DS21908A-page 1
MCP6S91/2/3
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
V
OUT
V
REF
V
SS
CS
SI
SO
SCK
V
DD
Analog Output
External Reference Pin
Negative Power Supply
SPI Chip Select
SPI Serial Data Input
SPI Serial Data Output
SPI Clock Input
Positive Power Supply
CH0, CH1 Analog Inputs
V
DD
– V
SS
........................................................................7.0V
All inputs and outputs..................... V
SS
– 0.3V to V
DD
+ 0.3V
Difference Input voltage ....................................... |V
DD
– V
SS
|
Output Short Circuit Current ..................................continuous
Current at Input Pin
.............................................................±2
mA
Current at Output and Supply Pins
................................ ±30
mA
Storage temperature .....................................-65°C to +150°C
Junction temperature .................................................. +150°C
ESD protection on all pins (HBM; MM)
................ ≥
4 kV; 200V
† Notice:
Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Function
Absolute Maximum Ratings †
DC CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R
L
= 10 kΩ to V
DD
/2, SI and SCK are tied low and CS is tied high.
Parameters
Amplifier Inputs (CH0, CH1)
Input Offset Voltage
Input Offset Voltage Mismatch
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Bias Current
Input Bias Current at
Temperature
Input Impedance
Input Voltage Range
Reference Input (V
REF
)
Input Impedance
Voltage Range
Amplifier Gain
Nominal Gains
DC Gain Error
DC Gain Drift
Note 1:
G = +1
G
≥
+2
G = +1
G
≥
+2
Sym
V
OS
∆V
OS
∆V
OS
/∆T
A
PSRR
I
B
I
B
I
B
Z
IN
V
IVR
Z
IN_REF
V
IVR_REF
G
g
E
g
E
∆G/∆T
A
∆G/∆T
A
Min
-4
—
—
70
—
—
—
—
V
SS
−
0.3
—
V
SS
—
-0.2
-1.0
—
—
Typ
—
0
±1.8
90
±1
30
600
10
13
||7
—
(5/G)||6
—
1 to 32
—
—
±0.0002
±0.0004
Max
+4
—
—
—
—
—
—
—
V
DD
+ 0.3
—
V
DD
—
+0.2
+1.0
—
—
Units
mV
µV
µV/°C
dB
pA
pA
pA
Ω||pF
V
kΩ||pF
V
V/V
%
%
%/°C
%/°C
(Note 2)
(Note 2)
G = +1
Conditions
Between inputs (CH0, CH1)
T
A
= -40°C to +125°C
G = +1
(Note 1)
CHx = V
DD
/2
CHx = V
DD
/2, T
A
= +85°C
CHx = V
DD
/2, T
A
= +125°C
+1, +2, +4, +5, +8, +10, +16 or +32
V
OUT
≈
0.3V to V
DD
−
0.3V
V
OUT
≈
0.3V to V
DD
−
0.3V
T
A
= -40°C to +125°C
T
A
= -40°C to +125°C
2:
3:
R
LAD
(R
F
+R
G
in Figure 4-1) connects V
REF
, V
OUT
and the inverting input of the internal amplifier. The MCP6S92 has
V
REF
tied internally to V
SS
, so V
SS
is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
recommended that the MCP6S92’s V
SS
pin be tied directly to ground to avoid noise problems.
The MCP6S92’s V
IVR
and V
IVR_REF
are not tested in production; they are set by design and characterization.
I
Q
includes current in R
LAD
(typically 60 µA at V
OUT
= 0.3V). Both I
Q
and I
Q_SHDN
exclude digital switching currents.
2004 Microchip Technology Inc.
DS21908A-page 2
MCP6S91/2/3
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R
L
= 10 kΩ to V
DD
/2, SI and SCK are tied low and CS is tied high.
Parameters
Ladder Resistance
Ladder Resistance
Ladder Resistance across
Temperature
Amplifier Output
DC Output Non-linearity G = +1
G
≥
+2
Maximum Output Voltage Swing
Sym
R
LAD
∆R
LAD
/∆T
A
Min
3.4
—
Typ
4.9
+0.028
Max
6.4
—
Units
kΩ
%/°C
(Note 1)
Conditions
T
A
= -40°C to +125°C
(Note 1)
V
ONL
V
ONL
V
OH_ANA
,
V
OL_ANA
I
SC
V
DD
V
DD_VAL
I
Q
I
Q_SHDN
—
—
V
SS
+ 20
V
SS
+ 60
—
2.5
—
0.4
—
±0.18
±0.050
—
—
±25
—
0.4
1.0
30
—
—
V
DD
– 100
V
DD
– 60
—
5.5
2.0
1.6
—
% of FSR V
OUT
≈
0.3V to V
DD
−
0.3V, V
DD
= 5.0V
% of FSR V
OUT
≈
0.3V to V
DD
−
0.3V, V
DD
= 5.0V
mV
G
≥
+2; 0.5V output overdrive
G
≥
+2; 0.5V output overdrive,
V
REF
= V
DD
/2
mA
V
V
mA
pA
Register data still valid
I
O
= 0
(Note 3)
I
O
= 0
(Note 3)
Short Circuit Current
Power Supply
Supply Voltage
Minimum Valid Supply Voltage
Quiescent Current
Quiescent Current, Shutdown
Mode
Note 1:
2:
3:
R
LAD
(R
F
+R
G
in Figure 4-1) connects V
REF
, V
OUT
and the inverting input of the internal amplifier. The MCP6S92 has
V
REF
tied internally to V
SS
, so V
SS
is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
recommended that the MCP6S92’s V
SS
pin be tied directly to ground to avoid noise problems.
The MCP6S92’s V
IVR
and V
IVR_REF
are not tested in production; they are set by design and characterization.
I
Q
includes current in R
LAD
(typically 60 µA at V
OUT
= 0.3V). Both I
Q
and I
Q_SHDN
exclude digital switching currents.
2004 Microchip Technology Inc.
DS21908A-page 3
MCP6S91/2/3
AC CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R
L
= 10 kΩ to V
DD
/2, C
L
= 60 pF, SI and SCK are tied low and CS is tied high.
Parameters
Frequency Response
-3 dB Bandwidth
Gain Peaking
Total Harmonic Distortion plus Noise
f = 20 kHz, G = +1 V/V
f = 20 kHz, G = +1 V/V
f = 20 kHz, G = +4 V/V
f = 20 kHz, G = +16 V/V
Step Response
Slew Rate
Sym
BW
GPK
THD+N
THD+N
THD+N
THD+N
Min
—
—
—
—
—
—
Typ
1 to 18
0
0.0011
0.0089
0.0045
0.028
Max
—
—
—
—
—
—
Units
MHz
dB
%
%
%
%
Conditions
All gains; V
OUT
< 100 mV
P-P
(Note 1)
All gains; V
OUT
< 100 mV
P-P
V
OUT
= 1.5V ± 1.0 V
PK
, V
DD
= 5.0V,
BW = 80 kHz, R
L
= 10 kΩ to 1.5V
V
OUT
= 2.5V ± 1.0 V
PK
, V
DD
= 5.0V,
BW = 80 kHz
V
OUT
= 2.5V ± 1.0 V
PK
, V
DD
= 5.0V,
BW = 80 kHz
V
OUT
= 2.5V ± 1.0 V
PK
, V
DD
= 5.0V,
BW = 80 kHz
G = 1, 2
G = 4, 5, 8, 10
G = 16, 32
f = 0.1 Hz to 10 Hz
(Note 2)
f = 0.1 Hz to 200 kHz
(Note 2)
SR
—
—
—
4.0
11
22
4.5
30
10
4
—
—
—
—
—
—
—
V/µs
V/µs
V/µs
µV
P-P
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Note 1:
2:
E
ni
e
ni
i
ni
—
—
—
—
nV/√Hz f = 10 kHz
(Note 2)
fA/√Hz f = 10 kHz
See Table 4-1 for a list of typical numbers and Figure 2-25 for the frequency response versus gain.
E
ni
and e
ni
include ladder resistance noise. See Figure 2-12 for e
ni
versus G data.
2004 Microchip Technology Inc.
DS21908A-page 4
MCP6S91/2/3
DIGITAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= 25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R
L
= 10 kΩ to V
DD
/2, C
L
= 60 pF, SI and SCK are tied low and CS is tied high.
Parameters
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
SPI Output (SO, for MCP6S93)
Logic Threshold, Low
Logic Threshold, High
SPI Timing
Pin Capacitance
Input Rise/Fall Times (CS, SI, SCK)
Output Rise/Fall Times (SO)
CS High Time
SCK Edge to CS Fall Setup Time
CS Fall to First SCK Edge Setup Time
SCK Frequency
SCK High Time
SCK Low Time
SCK Last Edge to CS Rise Setup Time
CS Rise to SCK Edge Setup Time
SI Setup Time
SI Hold Time
SCK to SO Valid Propagation Delay
CS Rise to SO Forced to Zero
Channel and Gain Select Timing
Channel Select Time
Sym
V
IL
I
IL
V
IH
—
Min
0
-1.0
0.7 V
DD
-1.0
Typ
—
—
—
—
Max
0.3V
DD
+1.0
V
DD
1.0
Units
V
µA
V
µA
Conditions
In Shutdown mode
V
OL_DIG
V
OH_DIG
C
PIN
t
RFI
t
RFO
t
CSH
t
CS0
t
CSSC
f
SCK
t
HI
t
LO
t
SCCS
t
CS1
t
SU
t
HD
t
DO
t
SOZ
t
CH
V
SS
V
DD
– 0.5
—
—
—
40
10
40
—
40
40
30
100
40
10
—
—
—
—
V
SS
+0.4
V
DD
—
2
—
—
—
—
10
—
—
—
—
—
—
80
80
V
V
I
OL
= 2.1 mA, V
DD
= 5V
I
OH
= -400 µA
All digital I/O pins
(Note 1)
MCP6S93
10
—
5
—
—
—
—
—
—
—
—
—
—
—
—
pF
µs
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
SCK edge when CS is high
V
DD
= 5V
(Note 2)
SCK edge when CS is high
MCP6S93
MCP6S93
—
1.5
—
µs
CHx = 0.6V, CHy = 0.3V, G = 1,
CHx to CHy select,
CS = 0.7 V
DD
to V
OUT
90% point
CHx = CHy = 0.3V,
G = 5 to G = 1 select,
CS = 0.7 V
DD
to V
OUT
90% point
CS = 0.7 V
DD
to V
OUT
90% point
CS = 0.7 V
DD
to V
OUT
90% point
Gain Select Time
t
G
—
1
—
µs
Shutdown Mode Timing
Out of Shutdown mode (CS goes high)
to Amplifier Output Turn-on Time
Into Shutdown mode (CS goes high) to
Amplifier Output High-Z Turn-off Time
Note 1:
2:
t
ON
t
OFF
—
—
3.5
1.5
10
—
µs
µs
Not tested in production. Set by design and characterization.
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t
DO
≤
80 ns), data input set-up time (t
SU
≥
40 ns), SCK high time (t
HI
≥
40 ns) and SCK rise and
fall times of 5 ns. Maximum f
SCK
is therefore
≈
5.8 MHz.
2004 Microchip Technology Inc.
DS21908A-page 5
