OKI Semiconductor
MD56V62320K
4-Bank
×
524,288-Word
×
32-Bit SYNCHRONOUS DYNAMIC RAM
PEDD56V62320K-01
Issue Date: Jan. 26, 2005
Preliminary
DESCRIPTION
The MD56V62320K is a 4-Bank
×
524,288-word
×
32-bit Synchronous dynamic RAM. The device
operates at 3.3 V. The inputs and outputs are LVTTL compatible.
FEATURES
•
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
• 4-Bank
×
524,288-word
×
32-bit configuration
•
Single 3.3 V power supply,
±0.3
V tolerance
•
Input : LVTTL compatible
•
Output : LVTTL compatible
•
Refresh : 4096 cycles/64 ms
•
Programmable data transfer mode
-
CAS
Latency (2, 3)
- Burst Length (1, 2, 4, 8, Full Page)
- Data scramble (sequential, interleave)
•
Auto-refresh, Self-refresh capability
• Lead Free Package:
86-pin 400 mil plastic TSOP (TypeII)
(
TSOPII86-P-400-0.80-K
)
(Product: MD56V62320K-xxTAZ03x)
xx indicates speed rank.
PRODUCT FAMILY
Max.
Family
Frequency
t
AC2
MD56V62320K-6TAZ03
MD56V62320K-7TAZ03
MD56V62320K-75TAZ03
MD56V62320K-10TAZ03
166MHz
143MHz
133MHz
100MHz
5.4ns
5.4ns
5.4ns
6ns
t
AC3
5.4ns
5.4ns
5.4ns
6ns
Access Time (Max.)
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PEDD56V62320K-01
OKI Semiconductor
MD56V62320K
PIN CONFIGURATION (TOP VIEW)
V
CC
1
DQ1 2
V
CC
Q 3
DQ2 4
DQ3 5
V
SS
Q 6
DQ4 7
DQ5 8
V
CC
Q 9
DQ6 10
DQ7 11
V
SS
Q 12
DQ8 13
NC 14
V
CC
15
DQM0 16
WE
17
CAS
18
RAS
19
CS
20
NC 21
BA0 22
BA1 23
A10/AP 24
A0 25
A1 26
A2 27
DQM2 28
V
CC
29
NC 30
DQ17 31
V
SS
Q 32
DQ18 33
DQ19 34
V
CC
35
DQ20 36
DQ21 37
V
SS
Q 38
DQ22 39
DQ23 40
V
CC
Q 41
DQ24 42
V
CC
43
86 V
SS
85 DQ16
84 V
SS
Q
83 DQ15
82 DQ14
81 V
CC
Q
80 DQ13
79 DQ12
78 V
SS
Q
77 DQ11
76 DQ10
75 V
CC
Q
74 DQ9
73 NC
72 V
SS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 V
SS
57 NC
56 DQ32
55 V
CC
Q
54 DQ31
53 DQ30
52 V
SS
Q
51 DQ29
50 DQ28
49 V
CC
Q
48 DQ27
47 DQ26
46 V
SS
Q
45 DQ25
44 V
SS
86-Pin Plastic TSOP(II)
(K Type)
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PEDD56V62320K-01
OKI Semiconductor
MD56V62320K
PIN DESCRIPTION
Pin Name
CLK
CS
CKE
A0–A10
BA0, BA1
RAS
CAS
WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
DQM#
DQ#
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Data Input/ Output Mask
Data Input/ Output
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
Note : The same power supply voltage must be provided to every V
CC
pin.
The same power supply voltage must be provided to every V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
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PEDD56V62320K-01
OKI Semiconductor
MD56V62320K
PIN DESCRIPTION
CLK
CS
Fetches all inputs at the “H” edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
UDQM and LDQM.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address
: RA0 – RA10
Column Address
: CA0 – CA7
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
CKE
Address
BA0, BA1
RAS
CAS
WE
Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the
clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H”
edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.
Data inputs/outputs are multiplexed on the same pin.
Functionality depends on the combination. For details, see the function truth table.
DQM0 - 3
DQ1 - 32
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PEDD56V62320K-01
OKI Semiconductor
MD56V62320K
BLOCK DIAGRAM
CKE
CLK
CS
RAS
CAS
WE
DQM0 - 3
Progra-m
ing
Register
Latency
& Burst
Controller
I/O
Controller
Timing
Register
Bank
Controller
BA0,BA1
Internal
Col.
Address
Counter
A0 - A10
BA0,BA1
Column
Address
Buffers
Column
Decoders
Input
Data
Register
32
88
8
Input
Buffers
32
Sense
Amplifiers
Internal
Row
Address
Counter
32
Read
Data
Register
32
Output
Buffers
32
DQ1
- DQ32
11
Row
Decoders
Row
Decoders
Word
Drivers
Word
Drivers
16Mb
Memory
Cells
16Mb
Memory
Cells
11
11
Row
Address
Buffers
Sense
Amplifiers
8
Column
Decoders
8
Column
Decoders
Sense
Amplifiers
11
Row
Decoders
Row
Decoders
Word
Drivers
Word
Drivers
16Mb
Memory
Cells
16Mb
Memory
Cells
11
Sense
Amplifiers
8
Column
Decoders
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