MDT10P622
1.General Description
This OTP-Based 8-bit micro-controller
uses a fully static CMOS technology
process to achieve higher speed and
smaller
chip
size
with
the
3K
low
power
of
consumption and high noise immunity. On
memory
includes
words
EPROM, and 128bytes of static RAM.
while PED is Disable
◆
Power Edge-detector Reset (PED)
◆
Interrupt capability
◆
Timer0:8-bit timer with 8-bit prescaler
(RTCC)
◆
Timer1:16bit timer with 16bit compare
register. This timer can be used as carrier
generator.
◆
4 Channel comparator
◆
Sleep mode for power saving.
◆
PB with port change wake- up interrupt
2.Features
◆
RISC CPU
◆
Fully static design
◆
37 single word instructions
◆
3K
×
14 program memory
◆
128 bytes RAM for data
◆
23 bi-directional I/O
◆
Eight level hardware stacks
◆
Watchdog timer (WDT) with on-chip RC
oscillator
◆
Power-On Reset (POR) ,only available
3.Applications
The application areas of this NEW MCU
range from appliance motor control and high
speed automotive to low power remote
transmitters/receivers and
telecommunications processors, such as
Remote controller, small instruments, toy ,
automobile and keyboard…etc.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.1
2006/7
Ver1.0
MDT10P622
4.
Pin Diagram
DIP/SOP
PA4/RTCC
VDD
PA5
VSS
PA6/INT
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PB4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 /MCLR
27 OSC1
26 OSC2
25 PC7
24 PC6/ VREF
23 PC5/CIC3
22 PC4/CIC2
21 PC3/CIC1
20 PC2/CIC0
19 PC1/T1OSI
18 PC0/T1OSO/T1SKI
17 PB7
16 PB6
15 PB5
VSS
PA4/RTCC
VDD
PA6/INT
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PB4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/MCLR
OSC1
OSC2
PC7
PC6/ VREF
PC5/CIC3
PC4/CIC2
PC3/CIC1
PC2/CIC0
PC1/T1OSI
PC0/T1OSO/T1SKI
PB7
PB6
PB5
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.2
2006/7
Ver1.0
MDT10P622
5. Pin function description
Pin name Type Buffer type
OSC1
OSC2
/MCLR
PA0
PA1
PA2
PA3
PA4
PA5
PA6(/INT)
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
TTL
TTL
ST
TTL
ST/TTL
Can be change pin function to be external interrupt pin
/int
Bi-directional I/O port B. Port B can be software
programmed for internal 100K ohm pull-up on all pins.
PB0-PB7 can generate interrupt on pin state change.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Vdd
Vss
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
TTL
TTL
TTL
TTL
TTL
TTL
Bi-directional I/O port C..
ST
ST
TTL
TTL
TTL
TTL
TTL
TTL
Power input
Ground pin
Can be Timer1 oscillator output or Timer1 clock input.
Can be Timer1 oscillator input.
TTL input level or Comparator input
TTL input level or Comparator input
TTL input level or Comparator input
TTL input level or Comparator input
TTL input level or Comparator VREF input
PB0 serial programming clock
PB1 serial programming data
PA4 Can be clock input
to RTCC input
.
Oscillator input
Oscillator out
Reset input
Bi-directional I/O port A. PA6 internal pull-high
80K ohm
Description
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.3
2006/7
Ver1.0
MDT10P622
6. Memory Mapping
6.1Program memory :
BANK 0
0000h
0001h
0002h
0003h
0004h Peripheral interrupt Vector
0005h
Program memory
(Page 0)
07FFh
0800h
Program memory
(Page 1)
0BFFh
Reset Vector
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
CCPR1L
CCPR1H
CCPR1C
TMR1L
TMR1H
T1CON
PSTA
PCHLAT
INTS
PIFB1
PCHLAT
INTS
PIEB1
IAR
RTCC
PCL
STATUS
MSR
PORT A
PORT B
PORT C
BANK 1
IAR
TMR
PCL
STATUS
MSR
CPIO A
CPIO B
CPIO C
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
OPTION2 90h
91h
92h
93h
94h
95h
96h
97h
98h
6.2Register file map :
1Fh
20h
General
Purpose
Register
7Fh
Unimplemented memory location.
9Fh
A0h
General
Purpose
Register
BFH
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.4
2006/7
Ver1.0
MDT10P622
BANK0
00
01
02
03
IAR (Indirect addressing register)
RTCC (Timer0) register
Program counter low byte
Status register
Bit
0
1
2
3
4
5
Symbol
C
DC
Z
PF
TF
Bank
Function
Carry
Digit carry
Zero flag
Power-down flag
WDT time-out flag
Register bank select (For direct addressing)
=0 Bank 0 (00h-7Fh)
=1 Bank 1 (80h-BFh)
General purpose bit
6:7
04
05
06
07
08
09
0A
0B
MSR (Memory select register)
PORTA (Port A data register)
PORTB (Port B data register)
PORTC (Port C data register)
Unimplemented.
Unimplemented.
PCHLAT (Program memory segment register)
INTS (Interrupt control register)
Bit
0
1
2
3
4
5
6
7
Function
PB port change interrupt flag bit.
/INT external interrupt flag bit.
RTCC(Timer0) overflow interrupt flag bit.
PB port change interrupt enable bit.
/INT external interrupt enable bit.
Timer0 overflow interrupt enable bit.
Peripheral interrupt enable bit.
Global interrupt enable bit.
Function
Timer1 overflow interrupt flag bit
Unimplemented. Always read as 0.
0C
PIFB1 (Peripheral interrupt flag register 1.)
Bit
0
7-1
0D
0E
Unimplemented.
TMR1L (Timer1 data register low byte.)
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.5
2006/7
Ver1.0
