128K x 8 FLASH
MFM8126S - 70/90/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
General Description
The MFM8126 is a 1Mbit CMOS 5.0V only FLASH
memory arranged as 128K X 8.
Flash memory combines the functionality of
EEPROM with on board electrical Write/Erasure,
which reliably stores data even after 10,000 cycles.
The device incorporates Automatic Programming
and Erase functions, thus simplifying the external
control circuitry.
In addition, a Sector Erase function is available
which can erase one 16K block of data randomly
and more than one block simultaneously. The
MFM8126 also features hardware sector
protection, which enables both program and erase
operations in any of the 8 sectors.
Features
• Fast Access Time of 70 / 90 / 120ns.
• Operating Power Read
165mW (Max)
Program/Erase 275mW (Max)
Standby Power
5.5mW (Max)
• JEDEC standard package.
• Four package styles.
• Flexible Sector Erase Architecture - 16K byte sector
size, with hardware protection of any number of sectors.
• Single Byte Program of 14µs (typical), Sector Program /
Verify time of 0.3 sec. (typical).
• Device FLASH Erase / Verify of 3 seconds (typical).
• Erase/Write Cycle Endurance 10,000 (minimum)
• Extended endurance (E) option
• Can be screened in accordance with MIL-STD-883.
Block Diagram
D0-D7
Vcc
Vss
Erase Voltage
Generator
Input/Output
Buffers
Pin Definitions
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8 TOP VIEW
V,S
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
W
E
NC
A14
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
WE
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CS
OE
Embedded
Algorithms
STB
Timer
Package Details
Pin Count
Description
32
32
32
32
Package Type
TM
Pin Functions
A0-A16
D0-D7
CS
WE
OE
Vcc
GND
0.1" Vertical-in-line (VIL )
0.6" Dual-in-line (DIL)
Leadless Chip Carrier (LCC)
J Leaded Chip Carrier (JLCC)
V
S
W
J
D7
CS
A10
OE
A11
A9
A8
A13
A14
21
22
23
24
25
26
27
28
29
D1
D2
GND
D3
D4
D5
D6
13
12
11
10
9
8
7
6
5
A0-A16
L
a
t
c
h
X-Decoder
Cell Matrix
D0
A0
A1
A2
A3
A4
A5
A6
A7
Vcc Detector
A
d
d
r
Y-Decoder
Y-Gating
14
15
16
17
18
19
20
TOP VIEW
J,W
4
3
2
1
32
31
30
A12
A15
A16
NC
VCC
WE
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
ISSUE 4.2 : November 1998
MFM8126S - 70/90/12
DC Operating Conditions
Absolute Maximum Ratings
(1)
Voltage on any pin w.r.t. Gnd (except A9)
Supply Voltage
(2)
Voltage on A
9
w.r.t. Gnd
Storage Temperature
Notes : (1)
(2)
max
unit
-2.0 to +7
V
-2.0 to +7
V
-2.0 to +14
V
-55 to +150 °C
(2)
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operationof the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied.
Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V. During
transitions voltage may overshoot by +/-2V for upto 20ns
Recommended Operating Conditions
Parameter
Symbol
min
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
TTL
CMOS
TTL
CMOS
V
CC
V
IH
V
IHC
V
IL
V
ILC
T
A
T
AI
T
AM
4.5
2.0
0.7 V
CC
-0.5
-0.5
0
-40
-55
typ
5.0
-
-
-
-
-
-
-
max
5.5
V
CC
+0.5
V
CC
+0.5
0.8
0.8
70
85
125
unit
V
V
V
V
V
°C
°C (-I suffix)
°C (-M,
MB
suffix)
DC Electrical Characteristics
(T
A
= -55°C to +125°C,V
CC
=5V
±
10%)
Parameter
Symbol Test Condition
Input Leakage Current
Output Leakage Current
Standby Supply Current
TTL
CMOS
I
LI
I
LO
I
SB1
I
SB2
I
CC1
I
CC2
V
OL
V
OH
V
LKO
V
ID
V
CC
=5.0V
V
IN
=0 to V
CC
, V
CC
= V
CC
max.
V
OUT
=0 to V
CC
,V
CC
= V
CC
max.
CS=V
IH
,V
CC
= V
CC
max.
CS=V
CC
+0.5 , V
CC
= V
CC
max.
CS = V
IL
, OE = V
IH
CS = V
IL
, OE = V
IH
I
OL
=12mA , V
CC
= V
CC
min.
I
OH
=-2.5mA
,
V
CC
= V
CC
min.
min
-
-
-
-
typ
-
-
-
-
max
±1
±1
1
100
30
50
Unit
µA
µA
mA
µA
mA
mA
V
V
V
V
Operating Current
Read
Program/Erase
Output LowVoltage
Output HighVoltage
Low Vcc lock out voltage
A9 voltage for autoselect
-
-
-
2.4
3.2
11.5
-
-
-
-
0.45
-
-
12.5
Capacitance
(T
A
=25
o
C,f=1MHz)
Parameter
Input Capacitance:
Output Capacitance:
Symbol
C
IN
C
OUT
Test Condition
V
IN
=0V
V
OUT
=0V
typ
6
8.5
max
7.5
12
Unit
pF
pF
Note: Capacitance calculated not measured.
2
MFM8126S - 70/90/12
ISSUE 4.2 : November 1998
AC Test Conditions
* Input pulse levels : 0.0V to 3.0V
* Input rise and fall times : 5 ns
* Input and output timing reference levels : 1.5V
* VCC = 5V +/- 10%
I/O Pin
166
Ω
1.76V
30pF
Operating Modes
The following modes are used to control the MFM8126
OPERATION
Auto-Select Manufacturer Code
Auto Select Device Code
Read
Standby
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
CS
L
L
L
H
L
L
L
L
OE
L
L
L
X
H
H
VID
L
WE
H
H
H
X
H
L
L
H
A
O
L
H
A0
X
X
A0
X
L
A
1
L
L
A1
X
X
A1
X
H
A
9
VID
VID
A9
X
X
A9
VID
VID
I /O
Code
Code
Dout
High Z
High Z
Din
X
Code
3
ISSUE 4.2 : November 1998
MFM8126S - 70/90/12
AC Operating Conditions
Read
Parameter
Read Cycle Time
Address to output delay
Chip Select to output
Output Enable to output
Chip Select to O/P High Z
Output Enable to output High Z
Output hold time
(From address,
CS or OE whichever occurs first)
Symbol
t
RC
t
AC
-70
min
max
70
-
-
-
-90
min
90
-
-
-
-
-
0
max
-
90
90
35
20
20
-
min
120
-
-
-
-
-
0
-12
max
-
120
120
50
30
30
-
unit
ns
ns
ns
ns
ns
ns
ns
-
70
70
30
20
20
-
t
CE
t
OE
t
DF
-
-
t
DF
t
OH
0
Write/ Erase/ Program
-70
Parameter
Write Cycle time
Address Setup time
Address Hold time
Data Setup Time
Data hold Time
Output Enable Setup Time
Output Enable Hold Time
Read Recover before Write
CS setup time
CS hold time
Write Pulse Width
Write Pulse Width High
Programming operation
Erase operation
(1)
Vcc setup time
(4)
Voltage Transition Time
(2,4)
Write Pulse Width
(2)
OE Setup time to WE active
(2,4)
CS Setup time to WE active
(3,4)
Notes:
(1)
(2)
(3)
(4)
Symbol
t
WC
t
AS
t
AH
t
DS
t
DH
t
OES
t
OEH
t
GHWL
t
CS
t
CH
t
WP
t
WPH
t
WHWH1
t
WHWH2
t
VCS
t
VLHT
t
WPP
t
OESP
t
CSP
min
70
0
45
30
0
0
0
0
0
0
35
20
14
3
50
4
10
4
4
max
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
-
-
-
-
min
90
0
45
40
0
0
0
0
0
0
40
20
14
3
50
4
10
4
4
-90
max
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
-
-
-
-
min
120
0
50
50
0
0
0
0
0
0
50
20
14
3
50
4
10
4
4
-12
max
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
-
-
-
-
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
µs
ns
ns
ns
ns
This also includes the preprogramming time.
These timings are for Sector Protect/Unprotect operations.
This timing is only for Sector Unprotect.
Not 100% tested.
4
MFM8126S - 70/90/12
ISSUE 4.2 : November 1998
Write/Erase/Program (Alternate CS controlled Writes)
-70
Parameter
Write Cycle time
Address Setup time
Address Hold time
Programming operation
Data hold Time
Output Enable Setup Time
Output Enable Hold Time
Read Recover before Write
WE setup time
WE hold time
CS Pulse Width
CS Pulse Width High
Programming operation
Erase operation
(1)
Vcc setup time
(2)
Notes:
Symbol
t
WC
t
AS
t
AH
t
DS
t
DH
t
OES
t
OEH
t
GHEL
t
WS
t
WH
t
CP
t
CPH
t
WHWH1
t
WHWH2
t
VCS
min
70
0
45
30
0
0
0
0
0
0
35
20
14
3
2
max
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
min
90
0
45
40
0
0
0
0
0
0
40
20
14
3
2
-90
max
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
min
120
0
50
50
0
0
0
0
0
0
50
20
14
3
2
-12
max
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
µs
(1) This also includes the preprogramming time.
(2) Not 100% tested.
5
