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MIC2584/2585
Micrel
MIC2584/MIC2585
Dual-Channel Hot Swap Controller/Sequencer
General Description
The MIC2584 and MIC2585 are dual-channel positive volt-
age hot swap controllers designed to facilitate the safe
insertion of boards into live system backplanes. The MIC2584
and MIC2585 are available in 16-pin and 24-pin TSSOP
packages, respectively. Using a few external discrete com-
ponents and by controlling the gate drives of external N-
Channel MOSFET devices, the MIC2584/85 provides inrush
current limiting and output voltage slew rate control in harsh,
critical power supply environments. Additionally, the MIC2585
provides output turn-on sequencing and output tracking
during turn-on and turn-off. In combination, the devices’
many features provide a simplified, robust solution for many
network applications to meet the power sequencing and
protection requirements of multiple-voltage logic systems.
Features
• 1.0V to 13.2V supply voltage operation
• Surge voltage protection up to 20V
• Current regulation limits inrush current regardless of
load capacitance
• Programmable inrush current limiting
• Electronic circuit breaker
• Dual-level overcurrent fault sensing eliminates false
tripping
• Fast response to short circuit conditions (< 1µs)
• Two sequenced output mode selections
(MIC2585 only)
•
∆250mV
supply tracking mode during turn-on/turn-off
(MIC2585 only)
• Overvoltage and undervoltage output monitoring
(Overvoltage for MIC2585 only)
• Undervoltage lockout protection
• /FAULT status output
• Power-On Reset and Power-Good status output
(Power-Good for MIC2585 only)
Applications
•
•
•
•
•
RAID systems
Network servers
Base stations
Network switches
Hot-board insertion
Ordering Information
Standard
Part Number
Pb-Free
MIC2584-xYTS
MIC2585-1xYTS
MIC2585-2xYTS
Output Sequencing
N/A
OUT2 follows OUT1
OUT1 follows OUT2
Fast Circuit Breaker
Threshold
x = J, 100mV
x = K, 150mV *
x = L, 200mV *
x = M, Off *
Package
16-pin TSSOP
24-pin TSSOP
MIC2584-xBTS
MIC2585-1xBTS
MIC2585-2xBTS
* Contact Micrel for availability.
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2005
1
MIC2584/2585
MIC2584/2585
Micrel
Typical Application
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
V
CC1
12V
D1
**BZX84Cxx
R1
10Ω
C1
0.47µF
R
SENSE2
0.020Ω
1
R
SENSE1
0.006Ω
1
3
2
4
Q1
Si7892DP
(PowerPAK™ SO-8)
C
LOAD1
330µF
R14
Q2
10.7kΩ
Si7892DP
1%
(PowerPAK™ SO-8)
V
OUT1
12V
6A
V
CC2
3.3V
D2
2
4
R2
10Ω
C2
0.47µF
3
C
LOAD2
330µF
C3
0.01µF
3
V
OUT2
3.3V
1.5A
R3
47kΩ
R4
22kΩ
R5
22kΩ
1
2
24
23
VCC2
SENSE2
VCC1
SENSE1
GATE2
8
R12
105kΩ
1%
ON
GATE1
OUT2
DIS2
22
5
6
7
R11
120Ω
C4
0.01µF
R15
4.42kΩ
1%
R10
560Ω
R13
14.7kΩ
1%
/FAULT
Signal
R6
130kΩ
1%
*C5
0.047µF
R8
30.9kΩ
1%
14
12
/FAULT
CDLY
MIC2585-1
FB2
FB1
OUT1
21
4
18
20
OV1
OV2
DIS1
PG1
PG2
/POR
TRK
9
19
17
16
15
R7
13kΩ
1%
DOWNSTREAM
CONTROLLER(S)
Downstream Control Signals
R9
8.06kΩ
1%
CPOR
10
GND
13
CFILTER
11
C6
0.02µF
C7
0.033µF
GND
Undervoltage (Output1) = 10.5V
Undervoltage (Output2) = 2.95V
Overvoltage (Input1) = 13.2V
Overvoltage (Input2) = 3.65V
START-UP Delay = 2.5ms
POR Delay = 10ms
Circuit Breaker Response Time = 16ms
*C5 (optional) is used to set the delay for V
OUT2
with respect to V
OUT1
V
OUT2
Delay = 9.5ms
**D1 is BZX84C18 and D2 is BZX84C8V2
Resistor tolerances are 5% unless specified otherwise.
Figure 1. Typical Application Circuit
MIC2584/2585
2
March 2005
MIC2584/2585
Micrel
VCC2 1
SENSE2 2
GATE2 3
OV2 4
24 VCC1
23 SENSE1
22 GATE1
21 OV1
20 OUT1
19 DIS1
18 FB1
17 PG1
16 PG2
15 /POR
14 /FAULT
13 GND
Pin Configuration
VCC2 1
SENSE2 2
GATE2 3
OUT2 4
FB2 5
ON 6
CPOR 7
CFILTER 8
16 VCC1
15 SENSE1
14 GATE1
13 OUT1
12 FB1
11 /POR
10 /FAULT
9 GND
OUT2 5
DIS2 6
FB2 7
ON 8
TRK 9
CPOR 10
CFILTER 11
CDLY 12
MIC2584
16-Pin TSSOP (TS)
MIC2585
24-Pin TSSOP (TS)
Pin Description
Pin Number
MIC2584
16
Pin Number
MIC2585
24
Pin Name
VCC1
Pin Function
Positive Supply (Input), Channel 1: This input is the main supply to the
internal circuitry and must be in the range of 2.3V to 13.2V. The GATE1 pin
is held low by an internal undervoltage lockout circuit until V
CC1
and V
CC2
exceed their respective undervoltage lockout threshold of 2.165V and 0.8V.
This input is protected up to 20V.
Positive Supply (Input), Channel 2: The GATE2 pin is held low by an
internal undervoltage lockout circuit until V
CC1
and V
CC2
exceed their
respective undervoltage lockout threshold of 2.165V and 0.8V. This input
must be in the range of 1.0V to 13.2V and less than or equal to V
CC1
. This
input is protected up to 20V.
Circuit Breaker Sense (Inputs): A resistor between this pin and VCC1 and
VCC2 sets the current limit threshold for each channel. Whenever the
voltage across either sense resistor exceeds the slow trip current limit
threshold (V
TRIPSLOW
), the GATE voltage is adjusted to ensure a constant
load current. If V
TRIPSLOW
(50mV) is exceeded for longer than time period
t
OCSLOW
, then the circuit breaker is tripped and both GATE outputs are
immediately pulled low. If the voltage across either sense resistor exceeds
the fast trip circuit breaker threshold, V
TRIPFAST
, at any point due to fast,
high amplitude power supply faults, then both GATE outputs are immediately
brought low without delay. To disable the circuit breaker for either channel,
the SENSE and VCC pins can be tied together.
The default V
TRIPFAST
for either device is 100mV. Other fast trip thresholds
are available: 150mV, 200mV, or OFF (V
TRIPFAST
disabled). Please contact
factory for availability of other options.
Enable (Input): Active High. The ON pin, an input to a Schmitt-triggered
comparator used to enable/disable the controller, is compared to a 1.235V
reference with 25mV of hysteresis. When a logic high is applied to the ON
pin (V
ON
> 1.235V), a start-up sequence begins when the GATE1 and
GATE2 pins begin ramping up towards their final operating voltage. When
the ON pin receives a logic low signal (V
ON
< 1.21V), the GATE pins are
grounded and /FAULT remains high if both inputs are above their respective
UVLO thresholds. The ON pin must be low for at least 20µs in order to
initiate a start-up sequence. Additionally, toggling the ON pin LOW to HIGH
resets the circuit breaker.
1
1
VCC2
2, 15
2, 23
SENSE2, SENSE1
6
8
ON
March 2005
3
MIC2584/2585
MIC2584/2585
Pin Number
MIC2584
3, 14
Pin Number
MIC2585
3, 22
Pin Name
GATE2, GATE1
Pin Function
Micrel
Gate Drive (Outputs): Connect each output to the gates of external
N-Channel MOSFETs. When ON is asserted, a 14µA current source is
activated and begins to charge the gate of the N-Channel MOSFET connected
to this pin. An internal clamp ensures that no more than 10V is applied
between the GATE and Source when VCC1 or VCC2 is above 5V. When the
circuit breaker trips or when an input undervoltage lockout condition is
detected, the GATE1 and GATE2 pins are immediately brought low.
Ground: Tie to analog ground.
Power-On Reset Timer (Input): A capacitor connected between this pin and
ground sets the start-up delay (t
START
) and the power-on reset interval
(t
POR
). Once the lagging supply rises above its UVLO threshold and ON
asserts, the capacitor connected to CPOR begins to charge. When the
voltage at CPOR crosses 0.3V, the start-up threshold (V
START
), a start cycle
is initiated as the GATE outputs begin to ramp while capacitor C
POR
is
immediately discharged to ground. When the voltage at the lagging FB pin
rises above its threshold (V
FB
), capacitor CPOR begins to charge again.
When the voltage at CPOR rises above the power-on reset delay threshold
(V
POR
) of 1.235V, the timer resets by pulling CPOR to ground and /POR is
deasserted. If C
POR
= 0, then t
START
defaults to 20µs.
Current Limit Response Timer (Input): A capacitor connected to this pin
defines the period of time, t
OCSLOW
, in which an overcurrent event must last
to signal a fault condition and trip the circuit breaker. When an overcurrent
condition occurs, a 2.5µA current source begins to charge this capacitor. If
the voltage at this pin reaches 1.235V, the circuit breaker is tripped, both
GATE pins immediately shut off, and /FAULT is asserted. If C
FILTER
= 0,
then t
OCSLOW
defaults to 20µs.
Power-Good Threshold Input (Undervoltage Detect): FB1 and FB2 are
internally compared to 1.235V and 0.80V references with 25mV of hyster-
esis, respectively. External resistive divider networks may be used to set the
voltage at these pins. If either FB input momentarily goes below its thresh-
old, then /POR is activated for one timing cycle, t
POR
, indicating an output
undervoltage condition. The /POR signal deasserts one timing cycle after the
FB pin exceeds its power-good threshold by 25mV. A 5µs filter on these pins
prevents glitches from inadvertently activating the /POR signal.
Circuit Breaker Fault Status (Output): Active-Low, weak pull-up to VCC1 or
open-drain. Asserted when the circuit breaker is tripped due to an
overcurrent, undervoltage lockout, or overvoltage event. When deasserted,
the MIC2585 will initiate a new start cycle by toggling the ON pin.
Power-On Reset (Output): Active Low, weak pull-up to VCC1 or open drain.
This pin remains asserted during start-up until a time period (t
POR
) after the
lagging FB pin threshold (V
FB1
or V
FB2
) is exceeded. The timing capacitor
C
POR
determines t
POR
. When the output voltage monitored at either FB pin
falls below V
FB
, /POR is asserted for a minimum of one timing cycle (t
POR
).
Output Voltage Monitor (Inputs): For output tracking, connect these pins to
their respective output to sense the output voltage.
Output Sequence Delay Timer (Input): This pin is internally clamped to 6V.
A capacitor connected to this pin sets a timer delay, t
DLY
, between V
OUT1
and V
OUT2
as shown in Figure 5. With this pin pulled up to VCC1 through a
resistor, and if C
GATE1
= C
GATE2
, both V
OUT1
and V
OUT2
ramp up and down
with the same dv/dt as depicted in the Tracking Mode diagram while
maintaining a maximum voltage differential between V
OUT1
and V
OUT2
.
Discharge Tracking Mode Pin (Input): Tie this pin to OUT1 or OUT2 to
enable tracking during turn-off cycle. Ground this pin to disable tracking
during turn-off. The TRK pin is not to be used as a digital input.
9
7
13
10
GND
CPOR
8
11
CFILTER
5, 12
7, 18
FB2, FB1
10
14
/FAULT
11
15
/POR
4, 13
N/A
5, 20
12
OUT2, OUT1
CDLY
N/A
9
TRK
MIC2584/2585
4
March 2005
