NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MNCEC
Rev. 0, 10/2019
MIMX8MN6DVTJZAA
MIMX8MN6DVTJZDA
MIMX8MN4DVTJZAA
MIMX8MN2DVTJZAA
MIMX8MN6DVTJZCA
MIMX8MN5DVTJZAA
MIMX8MN3DVTJZAA
MIMX8MN1DVTJZAA
i.MX 8M Nano
Applications Processor
Datasheet for Consumer
Products
Package Information
Plastic Package
FCBGA 14 x 14 mm, 0.5 mm pitch
Ordering Information
See
Table 2 on page 6
1
i.MX 8M Nano introduction
1. i.MX 8M Nano introduction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Recommended connections for unused input/output
12
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14
3.2. Power supplies requirements and restrictions . . . 22
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 26
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 29
3.7. Output buffer impedance parameters . . . . . . . . . 31
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 33
3.9. External peripheral interface parameters . . . . . . 34
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 68
4.2. Boot device interface allocation . . . . . . . . . . . . . . 68
5. Package information and contact assignments . . . . . . . 70
5.1. 14 x 14 mm package information . . . . . . . . . . . . 70
5.2. DDR pin function list . . . . . . . . . . . . . . . . . . . . . . 85
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
The i.MX 8M Nano application processor represents
NXP’s latest graphics and audio experience combining
state-of-the-art
media-specific
features
with
high-performance processing while optimized for lowest
power consumption.
The i.MX 8M Nano family of processors features
advanced implementation of a quad Arm® Cor-
tex®-A53 core, which operates at speeds of up to
1.5 GHz. A general purpose Cortex®-M7 running up to
750 MHz core processor is for real-time and low-power
processing.
The i.MX 8M Nano family of processors provides addi-
tional computing resources and peripherals:
• Advanced security modules for secure boot,
cipher acceleration and DRM support
• A wide range of audio interfaces, including I2S,
AC 97, TDM, and S/PDIF
• Large set of peripherals that are commonly used
in consumer/industrial market, including USB
and Ethernet
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
i.MX 8M Nano introduction
Table 1. Features
Subsystem
Cortex
®
-A53 MPCore platform
Feature
Quad symmetric Cortex
®
-A53 processors
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with Arm
®
NEON
TM
technology supporting the
Advanced Single Instruction Multiple Data architecture:
• Floating Point Unit (FPU) with support of the Arm
®
VFPv4-D16 architecture
Support of 64-bit Arm
®
v8-A architecture
512 KB unified L2 cache
Cortex
®
-M7 core platform
Low power microcontroller available for customer application:
• low power standby mode
• IoT features including Weave
• Manage IR or wireless remote
• ML inference applications (enhanced for i.MX 8M Nano)
Cortex
®
M7 CPU:
• 256 KB tightly coupled memory (TCM)
Connectivity
One USB 2.0 OTG controllers with integrated PHY interfaces:
• Spread spectrum clock support
Three Ultra Secure Digital Host Controller (uSDHC) interfaces:
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)
One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),
Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I
2
C modules
Three SPI modules
On-chip memory
Boot ROM (256 KB)
On-chip RAM (512 KB + 32 KB)
GPIO and pin multiplexing
General-purpose input/output (GPIO) modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
Power management
Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management
i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0, 10/2019
2
NXP Semiconductors
i.MX 8M Nano introduction
Table 1. Features (continued)
Subsystem
External memory interface
16-bit DRAM interfaces:
• LPDDR4-3200
• DDR4-2400
• DDR3L-1600
8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
eMMC 5.1 Flash (3 interfaces)
SPI NOR Flash (3 interfaces)
QuadSPI Flash with support for XIP (for Cortex
®
-M7 in low-power mode) and parallel
read mode of two identical FLASH devices
Multimedia
Graphic Processing Unit:
• GC7000UL with OpenCL and Vulkan support
• 2 shader
• 99.8 million triangles/sec
• 0.6 giga pixel/sec
• 9.6 GFLOPs 32-bit/19.2 GFLOPs 16-bit
• Supports OpenGL ES 1.1, 2.0, 3.0, OpenCL
• Core clock frequency of 600 MHz
• Shader clock frequency of 600 MHz
LCDIF Display Controller:
• Support up to 1080p60 display through MIPI DSI
MIPI Interfaces:
• 4-lane MIPI DSI interface
• 4-lane MIPI CSI interface
Audio:
• S/PDIF input and output, including a raw capture input mode
• Five external synchronous audio interface (SAI) modules supporting I2S, AC97,
TDM, codec/DSP, and DSD interfaces, comprising one SAI with 4 Tx and 4 Rx
lanes, two SAI with 2 Tx and 2 Rx lanes, and two SAI with 1 Tx and 1Rx lane. All
ports support 49.152 MHz BCLK.
• ASRC supports processing 32 audio channels, 4 context groups, 8 kHz to 384 kHz
sample rate and 1/16 to 8x sample rate conversion ratio.
• Pulse Density Modulation (PDM) input
Feature
i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0, 10/2019
NXP Semiconductors
3
i.MX 8M Nano introduction
Table 1. Features (continued)
Subsystem
Security
Feature
Resource Domain Controller (RDC):
• supports 4 domains and up to 8 regions of DDR
Arm
®
TrustZone
®
(TZ) architecture:
• Arm
®
Cortex-A53 MPCore TrustZone support
On-chip RAM (OCRAM) secure region protection using OCRAM controller
High Assurance Boot (HAB)
Cryptographic acceleration and assurance module (CAAM):
• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• Side channel attack resistance
• True random number generation (RNG)
• Manufacturing protection support
Secure non-volatile storage (SNVS):
• Secure real-time clock (RTC)
Secure JTAG controller (SJC)
System debug
Arm
®
CoreSight
TM
debug and trace technology
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex
®
-A53 and Cortex
®
-M7 CPUs
Cross Triggering Interface (CTI)
Support for 4-pin (JTAG) debug interface
NOTE
The actual feature set depends on the part numbers as described in
Table 2.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.
i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0, 10/2019
4
NXP Semiconductors
i.MX 8M Nano introduction
1.1
Block diagram
Figure 1
shows the functional modules in the i.MX 8M Nano applications processor system.
Security
TrustZone
DRM Ciphers
Secure Clock
eFuse Key Storage
Main CPU Platform
Quad Cortex®-A53
32 KB I-cache
NEON
32 KB D-cache
FPU
Connectivity
1 GB Ethernet
(IEEE1588, EEE, and AVB)
S/PDIF Rx and Tx
5x I2S/SAI
512 KB L2 Cache
Random Number
32 KB Secure RAM
Low Power, Security CPU
Cortex®-M7
4x UART
System Control
3x Smart DMA
XTAL
PLLs
3x Watchdog
LPDDR4/DDR4/DDR3L
4x PWM
6x Timer
4-lane MIPI-CSI Interface
Secure JTAG
NAND CTL (BCH62)
Temperature Sensor
ASRC
512 KB OCRAM
Dual-ch QuadSPI
4-lane MIPI-DSI Interface
eMMC 5.1/SD 3.0
Multimedia
3D Graphics: GC7000UL
256 KB TCM
4x I2C
3x SPI
1x USB 2.0 OTG and PHY
PDM
External Memory
Figure 1. i.MX 8M Nano system block diagram
i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0, 10/2019
NXP Semiconductors
5
