MK1491-06
AMD Geode™ Clock Source
Description
The MK1491-06 is a low-cost, low-jitter,
high-performance clock synthesizer for AMD’s
Geode-based computer and portable appliance
applications. Using patented analog Phased-Locked
Loop (PLL) techniques, the device accepts a 14.318
MHz crystal input to produce multiple output clocks. It
provides selectable PCI local bus and AC97 audio
clocks, 24 MHz and 48 MHz clocks for Super I/O and
USB, as well as multiple Reference outputs.
The device has multiple power-down modes to reduce
power consumption.
Features
•
Packaged in 28-pin SOIC or in 28-pin SSOP
•
Available in Pb (lead) free
•
Provides all critical timing for the AMD Geode
companion chip
•
•
•
•
•
•
•
•
Four PCI clocks
Selectable PCIF on up to 2 outputs
Early PCI clock selectability
Up to 4 Reference clocks
48 MHz USB and 24MHz SIO support
AC97 audio clock
Multiple power down modes
Low EMI Enable pin reduces EMI radiation on PCI
clocks (patented)
•
Operating voltage of 3.3 V ±5%
Block Diagram
VDD
6
GND
5
PCI Frequency Select
Low EMI Enable
PCIF Function Enable
Early PCI Enable
SLOW#
PCISTP#
PWRDWN#
Audio Select
2
3
PCI
Clocks
PCI
EPCI/PCI
Audio
Clock
Fixed
Clocks
16.394 MHz or
24.576 MHz or
49.152 MHz
48 MHz
MUX
14.318 MHz or
24 MHz
3
14.3M/24M Select
XI
14.31818 MHz
crystal
Crystal
Oscillator
14.318 MHz
XO
MDS 1491-06 J
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 110204
tel (408) 297-1201
●
www.icst.com
MK1491-06
AMD Geode™ Clock Source
Pin Assignment
VDD
XI
XO
GND
14.3M (TS)
14.3M
GND
14.3M (SEL AUDIO)
VDD
SLOW#
GND
FS
SEL24
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AC97 AUDIO (PEN)
PCI
VDD
PCI
PCI
GND
PCI (EPCI#)
48M (LE#)
VDD
24M/14.3M
VDD
GND
PCISTP#
PWRDWN#
PCI Frequency Select Table
TS
0
0
M
M
1
1
FS
0
1
0
1
0
1
PCI
Tristate all clocks
Reserved
30 MHz
33.3 MHz
25 MHz
37.5 MHz
24M/14.3M Frequency Select Table
SEL24
0
1
24.0 MHz
24M/14.3M
14.31818 MHz
PCIF Enable Control
PEN
Pin 25
PCI
PCI
PCIF
Pin 24
PCI
PCIF
PCIF
Early PCI Control Table
EPCI#
0
1
PCI (Pin 22)
1 ns early
Normal
0
M
1
PCIF continues to run in PCI STOP mode. See table on page
4.
EMI Control
LE#
0
1
ON
OFF
PCI Low EMI
AC97 Audio Frequency Select
SEL AUDIO
0
M
1
AC97 AUDIO
16.9344 MHz
24.576 MHz
49.152 MHz
Spread direction is DOWN.
Pin Descriptions
Pin
Number
1, 9, 14
2
3
4, 7, 11,
17, 23
5
6
Pin
Name
VDD
XI
XO
GND
14.3M (TS)
14.3M
Pin
Type
P
I
O
P
TI/O
O
Pin Description
Connect to +3.3 V. Must be same voltage on all pins.
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
Crystal connection. Connect to a 14.31818 MHz crystal, or leave
unconnected for clock.
Connect to Ground.
14.318 MHz output. Input control for all clocks per table above.
14.318 MHz buffered reference clock output.
MDS 1491-06 J
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 110204
tel (408) 297-1201
●
www.icst.com
MK1491-06
AMD Geode™ Clock Source
Pin
Number
8
10
12
13
15
16
18, 20, 26
19
21
22
24
25
27
28
Pin
Name
14.3M (SEL
AUDIO)
SLOW#
FS
SEL24
PWRDWN#
PCISTP#
VDD
24M/14.3M
48 (LE#)
PCI (EPCI#)
PCI
PCI
PCI
AC97 AUDIO
(PEN)
Pin
Type
TI/O
I
I
I
I
I
P
O
I/O
I/O
O
O
O
TI/O
Pin Description
14.318 MHz output and audio frequency select input per table above.
PCI normal or slow mode select input per table on page 4.
Frequency Select for PCI clocks per table above.
Fixed frequency select input per table above. Selects frequency on pin
19.
Power down control; defined in table on page 4.
PCI Stop power down control; defined in table on page 4.
Connect to +3.3 V. Must be same voltage on all pins.
Fixed frequency clock output per table above.
Fixed frequency clock output and low EMI (spread spectrum) enable
input per table above.
PCI Output clock that can be early. Input control for Early PCI per table
above.
PCI Output clock. PCI/PCIF control set by PEN per table above.
PCI Output clock. PCI/PCIF control set by PEN per table above.
PCI Output clock.
Audio clock output and PCIF Function Enable per table above.
KEY:
I = Input
TI = Tri-level
O = Output
P = Power supply connection
(T)I/O = Input on power up, becomes an Output after 10 ms
Weak internal pull-up resistors are present on SEL24, EPCI#, FS, LE#, PCISTP#, and SLOW#. These pins
should be tied to VDD or GND, and not be left floating. Internal resistors on PEN, SEL AUDIO, and TS pull
to mid-level (M).
MDS 1491-06 J
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 110204
tel (408) 297-1201
●
www.icst.com
MK1491-06
AMD Geode™ Clock Source
Power Down Control Table
PCISTP# PWRDWN# SLOW#
X
0
0
1
X
X
MODE
Power down
PCI STOP
PCI
LOW
LOW
PCIF
LOW
ON
24/14.3
LOW
ON
14.3
LOW
ON
Description
All outputs low. PLL’s
and oscillators off.
PCI clocks
synchronously enter
and leave low state.
All clocks on.
1
1
X
ON
ON
ON
ON
ON
Key: 1 = connected to VDD, 0 = connected to ground, X = any valid logic level, combination inputs/outputs
should be connected to VDD or ground through a 10 kΩ resistor as shown below.
Power-on Default Conditions
Pin #
5
8
10
12
13
15
16
21
22
28
Function
TS
SEL AUDIO
SLOW#
FS
SEL 24
PWRDWN#
PCISTP#
LE#
EPCI#
PEN
Default
M
M
1
1
1
1
1
1
1
M
All outputs enabled.
Condition
Audio clock (pin 28) set to 24.576 MHz
PCI clocks set to 33.3 MHz. Refer to Power Down Control Table above.
PCI frequency = 33.3 MHz.
24M/14.3M (pin 19) set to 24 MHz.
All clocks running.
PCI clocks running.
Low EMI function OFF
Pin 22 set to normal PCI signal (not early).
PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock
(33.33 MHz).
MDS 1491-06 J
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 110204
tel (408) 297-1201
●
www.icst.com
MK1491-06
AMD Geode™ Clock Source
External Components
The MK1491-06 requires some inexpensive external
components for proper operation. Decoupling
capacitors of 0.1µF should be connected on each VDD
pin to ground, as close to the MK1491-06 as possible.
A series termination resistor of 33Ω may be used for
each clock output. See the discussion below for other
external resistors required for proper I/O operation. The
14.3 MHz oscillator has internal caps that provide the
proper load for a parallel resonant crystal with CL=18
pF. For tuning with other values of C
L
, the formula
2*(C
L
-18) gives the value of each capacitor that should
be connected between X1 and ground and X2 and
ground.
I/O Structure
The MK1491-06 provides more functionality in a 28-pin
package by using a unique I/O technique. The device
checks the status of all I/O pins during power-up and at
exit from the Power Down state. This status (pulled
high, low, or mid-level) then determines the frequency
selections and power down modes (see the tables on
pages 2 and 4). Within 10ms after power up, the inputs
change to outputs and the clocks start up. In the
diagrams to the right, the 33Ω resistors are the normal
output termination resistors. The 10kΩ resistor pulls
low to generate a logic zero. Weak internal pull-up
resistors are present on SEL24, EPCI#, FS, LE#,
PCISTP#, and SLOW#. These pins should be
connected directly to VDD or GND if not under active
control. Internal resistors on PEN, SEL AUDIO, and TS
pull to a mid-level (M).
33
For select
= 0 (low)
I/O
10 k
Do not stuff for
“1” selection
To load*
*Note: Do not use a TTL load. This will overcome the
10 kΩ pull-down and force the input to a logic 1.
MDS 1491-06 J
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 110204
tel (408) 297-1201
●
www.icst.com
FPGA/CPLD
