OKI Semiconductor
ML2216-XXX/ML22P16
Oki ADPCM2 Algorithm-Based Speech Synthesis LSI
FEDL2216DIGEST-03
Issue Date: Nov. 15, 2007
GENERAL DESCRIPTION
The ML2216-XXX is speech synthesis device with a 8Mbit P2ROM built-in.
The ML2216-XXX incorporates ADPCM2 decoder, 12-bit D/A converter, and low-pass filter. Moreover, the
monophonic speaker amplifier for driving a direct speaker is built in.
The ML2216-XXX carried out all functions required for a voice response circuit to one chip. For this reason,
inclusion to small and pocket equipment became still easier.
ML2216-xxx serves as write-in shipment.
ML22P16 is speech synthesis device with 8M bit OTP memory built-in. User is able to program a device one time
by using exclusive tool.
FEATURES
•
Built-in memory capacity and the Maximum playback time length (please refer to the following table)
Type
ML2216/ML22P16
ROM capacity
8 Mbit
Maximum playback time length (sec) (In 4-bit ADPCM2)
F
SAM
= 4.0 kHz
F
SAM
= 8.0 kHz
F
SAM
= 16 kHz
524
262
131
•
Non-linear 8-bit PCM, 8-bit PCM, 16-bit PCM, and 4-bit ADPCM2 algorithms
•
Sampling frequency:
4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz
•
12-bit D/A converter built in
•
Built-in low-pass filter:
Digital filter
•
Amplifier built-in for a speaker drive: 0.3W 8Ω(At VDD=5.0V)
•
CPU interface:
3 line type serial clock synchronization
•
Maximum number of phrases:
256 phrases
•
Volume control function:
VOLUME command (16 step / OFF)
•
Repeat function:
LOOP command
•
Master clock frequency:
4.096 MHz
•
Power supply voltage:
2.7V to 3.6V or 4.5V to 5.5V
•
Operating temperature:
-20°C to +85°C
•
Package:
44-pin plastic QFP (QFP44-P-910-0.80-2K)
(ML2216-XXXGA, ML22P16GA)
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ML2216/ML22P16
Table below summarizes the points of difference between the ML2250 family and the ML2216/ML22P16.
ML2250 family
Parallel or serial
2-bit ADPCM2
4-bit ADPCM2
8-bit PCM
8-bit non-linear PCM
16-bit PCM
256
4.0/5.3/6.4/8.0/10.7/12.8/16.0/21.3/25.
6/32.0/42.7/48.0
4.096 MHz
Voltage type: 14 bits
FIR type interpolation filter
None
2 channels
Both 2 channels without user definable
phrase restrictions
29 steps
(–2 dB/–5 dB steps)
built-in(4ms to 1024ms)
No limit
in
0 (Note)
External data input possible
44-pin plastic QFP
ML2216/ML22P16
Serial
4-bit ADPCM2
8-bit PCM
8-bit non-linear PCM
16-bit PCM
256
4.0/5.3/6.4/8.0/10.7/12.8/16.0
4.096 MHz
Current type: 12 bits
Secondary comb filter
built-in
1 channel
1 channel without user definable phrase
restrictions
16 steps
built-in(20ms to 1024ms)
No limit
0 (Note)
—
44-pin plastic QFP
Interface
Playback method
Max. number of phrases
Sampling frequency (kHz)
Clock frequency
D/A converter
Low-pass filter
Amplifier for a speaker drive
Number of channels
Phrase control table
Volume adjustment
Silent insertion function
Repeat function
Seam silence interval
continuous playback
Others
Package
Note: Continuous playback shown in the figure below is possible.
1 phrase
1 phrase
No silence interval
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OKI Semiconductor
ML2216/ML22P16
BLOCK DIAGRAM
RAO
RAI
Address Controller
DV
DD
DGND
Phrase Address
Latch
20bit Multiplexer
8Mbit ROM
V
PP
20bit
Address Counter
ADPCM Synthesizer
CS
SCK
DI
BUSY
NCR
DIPH
LPF
I/O
Interface
VBG
PCM Synthesizer
12bit DAC
3.3V Regulator
REGO
VBG
SG
OSC
Timing
Controller
SPV
DD
SPGND
XT XT RESET
TEST
AV
DD
AGND AOUT
SPIN
SPM
SPP
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ML2216/ML22P16
PIN CONFIGURATION (TOP VIEW)
44-pin plastic QFP
NC 1
SPV
DD
2
SPP 3
SPM 4
SPGND 5
SPIN 6
AGND 7
AOUT 8
SG 9
DGND 10
NC 11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
DGND
RAO
RAI
DGND
XT
XT
DV
DD
NC
NCR
BUSY
DI
SCK
CS
RESET
DIPH
VPP
DGND
VBG
AV
DD
NC
NC
DV
DD
DGND
REGO
NC
NC
SCAN
TEST
NC: No Connection
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ML2216/ML22P16
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
reset input pin.
At “L” level input, the device enters the initial state.
During reset input, operation of all circuits stops and it will be in a power
down state.
Input the "L" level at the time of a power supply injection. After power
supply voltage is stabilized, please make it "H" level.
CPU interface chip select pin.
A serial interface becomes effective on the "L" level.
serial clock input pin.
serial data input pin.
A DIPH pin chooses the timing which takes in serial data inside LSI.
When a DIPH pin is the "L" level, DI input data is taken in inside LSI by
the rising edge of a SCK clock.
When a DIPH pin is "H" level, DI input data is taken in inside LSI by the
falling edge of a SCK clock.
A
BUSY
pin outputs the signal which shows a phrase reproduction
state.
The "L" level is outputted during reproduction.
A NCR pin outputs the signal which shows the input permission state of
a command.
When the NCR pin is "H" level ,a command input is possible.
When the NCR pin is the "L" level ,a command input cannot be
performed.
Wired to a crystal or ceramic oscillator.
A feedback resistor of around 1 M
Ω
is built in between this XT pin and
XT
pin (pin 35).
When using an external clock, input the clock from this pin.
When you use a crystal or ceramic oscillator, please connect with the
latest of LSI as much as possible.
Wired to a ceramic or crystal oscillator.
When using an external clock, keep this pin open.
When you use a crystal or ceramic oscillator, please connect with the
latest of LSI as much as possible.
Regulator output pin.
It becomes the power supply of Built-in P2ROM.
Insert a 10
µ
F or larger capacitor between this pin and DGND pin.
Standard voltage output pin for 3.3V regulators.
Insert a 0.1
µ
F capacitor between this pin and DGND pin.
Standard voltage output pin of built-in speaker amplifier.
Insert a 0.1
µ
F or larger capacitor between this pin and AGND pin.
Analog output pin.
When you input into built-in speaker amplifier, insert a 10
µ
F capacitor
between this pin and SPIN pin.
26
RESET
I
27
28
29
CS
I
I
I
SCK
DI
25
DIPH
I
30
BUSY
O
31
NCR
O
34
XT
I
35
XT
O
18
REGO
O
12
9
VBG
SG
O
O
8
AOUT
O
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模拟电子