FEDL22420-06
Issue Date: Oct.10, 2013
ML22420MB/ML22460MB
Speech Synthesis LSI with Serial ROM Interface Including 4-Channel Mixing Function
GENERAL DESCRIPTION
ML22420 and ML22460 are voice synthesis LSIs with serial interface to the external ROM that stores voice
data.
These LSIs include edit ROM, ADPCM2 decoder, 16-bit DA converter, low pass filter and monaural speaker
amplifier. Also, ML22420 supports the synchronous serial interface and ML22460 supports the I2C interface.
By integrating all the functions required for voice output into a single chip, these LSIs can be more easily
incorporated in compact portable devices.
•
Maximum External ROM capacity:
128Mbits
•
External ROM capacity and maximum vocal reproduction time:
(at the case of 4-bit ADPCM2 algorithm)
External
ROM capacity
128 Mbits
64 Mbits
16 Mbits
Maximum vocal reproduction time (sec)
F
S
= 4.0 kHz
F
S
= 8.0 kHz
F
S
= 16 kHz
8,352
4,176
2,088
4,176
1,044
2,088
522
1,044
261
4-bit ADPCM2
8-bit Nonlinear PCM
8-bit PCM, 16-bit PCM
Can be specified for each phrase.
4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 /
•
Sampling frequency(F
S
):
48.0 kHz
F
S
can be specified for each phrase.
•
Built-in low-pass filter and 16-bit DA converter
•
Speaker driving amplifier:
0.7 W (when Z=8Ω , DV
DD
=5 V, Ta=25°C)
2ch analog inputs (internal: 1ch, external: 1ch)
•
CPU command interface:
3-wired serial clock-synchronized (ML22420)
I2C interface (ML22460)
•
Maximum number of phrases:
1024 phrases from 000h to 3FFh
•
Volume control:
32 levels (OFF is included) can be set by CVOL command.
50 levels (OFF is included) can be set by AVOL command.
•
Repeat function:
LOOP commands
•
4-channel mixing function:
Available when F
S
for each channel is 16kHz or less
•
Master clock frequency:
4.096 MHz
•
Power supply voltage:
2.7 V to 5.5 V
•
Operating temperature range:
–40°C to +85°C
•
Package:
30-pins plastic SSOP (SSOP30-P-56-0.65-K-MC)
•
Product name:
ML22420, ML22460
•
Voice synthesis method:
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FEDL22420-06
ML22420MB/ ML22460MB
The following table shows the differences among the other speech synthesis LSIs.
Item
CPU interface
Voice memory
Memory interface
Voice synthesis
algorithm
Maximum number
of phrases
Sampling
frequency (kHz)
Clock frequency
D/A converter
Low-pass filter
Speaker driving
amplifier
Edit ROM function
Simultaneous
sound production
function (mixing
function)
Volume control
Silence insertion
Repeat function
Silent interval for
seam during
continuous
playback (*1)
Power supply
voltage
Package
MSM9841
Parallel
external
8/16-bits parallel
4-bit ADPCM2
8-bit nonlinear PCM
8-bit straight PCM
16-bit straight PCM
-
4.0/ 6.4/ 8.0/
12.8/ 16.0/ 32.0
4.096MHz
(with a built-in crystal
oscillator circuit)
14 bits
2nd order comb. filter
N.A.
Available
Monaural
8 levels
N.A.
Available
No
(Seamless)
2.7 V to 5.5 V
56-pins QFP
ML2240
Parallel/Serial
←
8-bits parallel
←
ML22420/460
Serial/I2C
←
Serial
←
256
4.0/ 5.3/ 6.4/
8.0/ 10.7/ 12.8/
16.0
←
←
FIR interpolation filter
N.A.
←
4-channels
29 levels
20 ms to 1024 ms
(4 ms step)
←
←
1024
4.0/5.3/6.4/8.0/10.6/
12.0/12.8/16.0/21.3/
24.0/25.6/32.0/48.0
←
16 bits
←
Built-in 0.7W
(8Ω, DV
DD
= 5 V)
←
←
32 levels
←
←
←
←
80-pins TQFP
←
30-pins SSOP
*1: Continuous playback as shown below is possible.
1 phrase
1 phrase
No silent interval
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FEDL22420-06
ML22420MB/ ML22460MB
BLOCK DIAGRAMS
(ML22420MB : Synchronous serial interface)
PSCK PCSB PSI PSO
DV
DD
DGND
V
DDL
Address Controller
Multiplexer
Serial ROM
Interface
Phrase Address
Latch
CSB
SCK
SI
SO
CBUSYB
DIPH
TESTI
RESETB
TESTO
(0, 1, 2)
Address Counter
ADPCM Synthesizer
PCM Synthesizer
I/O
Interface
Timing
Controller
16bit DAC
LPF
OSC
SP-AMP
XT XTB
SPV
DD
SPGND
AIN SPM SPP
SG
(ML22460MB : I2C interface)
PSCK PCSB PSI PSO
DV
DD
DGND
V
DDL
Address Controller
Multiplexer
Serial ROM
Interface
Phrase Address
Latch
SAD2
SAD1
SAD0
SCL
SDA
CBUSYB
TESTI
RESETB
TESTO
(0, 1, 2)
Address Counter
ADPCM Synthesizer
PCM Synthesizer
I/O
Interface
Timing
Controller
16bit DAC
LPF
OSC
SP-AMP
XT XTB
SPV
DD
SPGND
AIN SPM SPP
SG
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FEDL22420-06
ML22420MB/ ML22460MB
PIN CONFIGURATIONS (TOP VIEW)
(ML22420MB : Synchronous serial interface)
AIN
TESTI
RESETB
TESTO0
DIPH
TESTO1
TESTO2
DGND
CSB
SCK
SI
SO
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPV
DD
SG
PCSB
PSCK
NC
DV
DD
V
DDL
NC
PSI
PSO
DV
DD
XTB
NC:No Connection
30-Pin Plastic SSOP
(ML22460MB : I2C interface)
AIN
TESTI
RESETB
TESTO0
SAD0
TESTO1
TESTO2
DGND
SAD1
SCL
SDA
SAD2
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPV
DD
SG
PCSB
PSCK
NC
DV
DD
V
DDL
NC
PSI
PSO
DV
DD
XTB
NC:No Connection
30-Pin Plastic SSOP
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FEDL22420-06
ML22420MB/ ML22460MB
PIN DESCRIPTION (COMMON TO ALL PRODUCTS)
Pin
1
2
Symbol
AIN
TESTI
I/O
I
I
Initial value
Description
(*1)
0
Input pin for speaker amplifier.
Input pin for testing.
0
Fix this pin to “L” level (DGND level). This pin has a pull-down resistor
built in.
Input pin for reset.
At the “L” level, the LSI enters initial state. During reset, the entire
circuitry stops and enters power down state. Input “L” level when
0
power is supplied. After the power supply voltage is stable, drive this
(*2)
pin to “H” level. Then the entire circuitry can be powered up.
This pin has a pull-up resistor built in.
Output pins for testing.
Hi-Z
Leave these pins open.
—
Ground pins for logic circuitry.
Output pin for command processing status.
1
This pin outputs “L” level during command processing. Any command
should be entered when this pin is “H” level.
Connect to the crystal or ceramic resonator.
A feedback resistor around 1 MΩ is built in between this pin and the
0
XTB pin. Use this pin if need to use an external clock.
If the resonator is used, connect it as close to this pin as possible.
Connect to the crystal or ceramic resonator.
1
When to use an external clock, leave this pin open.
If the resonator is used, connect it as close to this pin as possible.
Power supply pins for logic circuitry.
—
Connect a capacitor of 0.1μF or more between these pins and DGND
pins.
1
Serial data output pin for voice ROM interface.
Hi-Z
Serial data input pin for voice ROM interface.
Non connected pins. Leave these pins open.
—
O
O
—
—
—
O
O
—
1
1
0
—
—
0
Hi-Z
Regulator output pin for internal logic circuitry.
Connect a capacitor recommended between this pin and DGND pin.
Clock output pin for voice ROM interface.
Chip select output pin for voice ROM interface.
At the “L” level, ROM access is available.
Reference voltage output pin for the speaker amplifier built-in.
Connect a capacitor recommended between this pin and DGND pin.
Power supply pin for the speaker amplifier.
Connect a bypass capacitor of 0.1μF or more between this pin and
SPGND pin.
Ground pin for the speaker amplifier.
Positive(+) output pin of the speaker amplifier built-in.
Serves as the LINE output (*3), if built-in speaker amplifier is not used.
Negative(-) output pin of the speaker amplifier built-in.
3
RESETB
I
4,6,7
8,14
13
TESTO
(0,1,2)
DGND
CBUSYB
O
—
O
15
XT
I
16
XTB
O
17, 22
18
19
20,23
21
24
25
26
27
28
29
30
DV
DD
PSO
PSI
N.C.
V
DDL
PSCK
PCSB
SG
SPV
DD
SPGND
SPP
SPM
—
O
I
*1: Indicate the initial value during reset input or power down.
*2: “H” during power down.
*3: Output a voice signal before amplified by the speaker amplifier built-in.
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