FEDL610Q346DIGEST-01
Issue Date: January 7, 2010
ML610Q346/ML610346
8-bit Microcontroller with Voice Output Function
GENERAL DESCRIPTION
Equipped with an OKI SEMICONDUCTOR original 8-bit CPU nX-U8/100, the ML610Q346/ML610346 is a
high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as an op-amp,
12-bit A/D converter, timer, synchronous serial port, UART, and voice output function. The nX-U8/100 CPU is
capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel
processing by the 3-stage pipelined architecture. The microcontroller is also equipped with a flash memory that
has achieved low voltage and low power consumption (at read) equivalent to mask ROMs, so it is best suited to
battery-driven applications such as cellular phones. In addition, it has an on-chip debugging function, which
allows software debugging/rewriting with the LSI mounted on the board.
FEATURES
•
CPU
−
8-bit RISC CPU (CPU name: nX-U8/100)
−
Instruction repertoire: 16-bit length instructions
−
Instruction set: Transfer, arithmetic operations, comparison, logical operations, multiply/divide operations,
bit manipulation, bit logical operations, jump, conditional jump, call return stack manipulation, and
arithmetic shift instructions.
−
Built-in on-chip debugging function
−
Minimum instruction execution time:
31.25
μs
(@ 32kHz system clock)
0.244
μs
(@ 4.096 MHz system clock)
•
Internal memory
−
ML610Q346
Has 128-Kbyte flash memory (64K
×
16-bit) built in. (including unusable 1KByte TEST area)
−
ML610346
Has 128-Kbyte mask memory (64K
×
16-bit) built in. (including unusable 1KByte TEST area)
−
Has 1-Kbyte RAM (1024
×
8-bit) built in.
•
Interrupt controller
−
Non-maskable interrupt: 2 sources (1 internal source and 1 external sources)
−
Maskable interrupt: 18 sources (10 internal sources and 8 external sources)
•
Time-base counter
−
Low-speed side time-base counter
×
1ch
−
High-speed side time-base counter
×
1ch
•
Watchdog timer
−
Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
−
Free-running
−
Selectable overflow period: 4 types (125 ms, 500 ms, 2 sec, 8 sec)
•
Timer
−
8-bit
×
2ch (16-bit configuration also enabled)
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FEDL610Q346DIGEST-01
ML610Q346/346
•
Voice output function
−
Voice synthesis method: HQ-ADPCM / 4-bit ADPCM2 / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
−
Sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 kHz
•
Speaker amplifier output power
−
1W(at 5V)
•
Synchronous serial port
−
Master/slave selectable
−
LSB/MSB-first selectable
−
8-bit/16-bit length selectable
•
UART
−
Half-Duplex Communication
−
TXD/RXD
×
1 channel
−
Bit length, with/without parity, odd/even parity, 1 or 2 stop bits
−
Positive/negative logic selectable
−
Built-in baud-rate generator
•
Successive-approximation type A/D converter
−
12-bit A/D converter
−
Input: 3ch
−
Conversion time: 26.86
μs
per channel at 4.096 MHz
•
Op-amp
−
3ch
−
Composition is possible as reversal amplifier, reversed amplifier, and a comparator.
•
General-purpose port
−
Input-only port
×
8ch
−
Output-only port
×
4ch (those as secondary functions are also included)
−
Input-output port
×
16ch (those as secondary functions are also included)
•
Reset
−
Resetting by the RESET_N pin
−
Resetting upon power-on detection
−
Resetting upon WDT overflow detection
•
Clock
−
Low-speed side clock
Built-in RC oscillator (32 kHz)
−
High-speed side clock
Crystal/ceramic oscillation (4.096 MHz), external clock
•
Power management
−
HALT mode: Halts the execution of instructions issued by the CPU (the peripheral circuits continue
operating)
−
STOP mode: Stops low-speed and high-speed oscillation (the CPU and the peripheral circuits stop
operating)
−
Clock gear: Allows changing the frequency of the high-speed system clock by software (oscillator clock
divided by 1, 2, 4, or 8)
−
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused
peripherals.
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FEDL610Q346DIGEST-01
ML610Q346/346
•
Shipment
−
64-pin TQFP
−
High-speed side clock
：Crystal/ceramic
oscillation (4.096 MHz)
Flash Memory
：ML610Q346-xxxTB
(blank product: ML610Q346-NNNTB)
Mask Memory
：ML610346-xxxTB
−
High-speed side clock
：external
clock
Flash Memory
：ML610Q346J-xxxTB
(blank product: ML610Q346J-NNNTB)
Mask Memory
：ML610346J-xxxTB
xxx: ROM code number
•
Guaranteed operating range
−
Operating temperature:
−40°C
to +85°C
−
Operating voltage: V
DD
= 2.2 to 5.5 V, SPV
DD =
2.3 to 5.5 V, AV
DD
= 2.2 to 5.5 V
(Be sure to apply the same voltage to V
DD
and SPV
DD
power supplies.)
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FEDL610Q346DIGEST-01
ML610Q346/346
BLOCK DIAGRAM
Figure 1 is a block diagram of the ML610Q346.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding
port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
（Flash）
128Kbyte
V
PP
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
OSC0
OSC1
LSCLK*
OUTCLK*
RESET &
TEST
Data-bus
INT
1
SSIO
SCK0*
1
SIN0*
1
SOUT0*
RXD0*
1
TXD0*
1
1
RAM
1024byte
INT
1
UART
OSC
RC32K
INT
4
Interrupt
Controller
INT
9
NMI
P00 to P07
GPIO
P20 to P23
P30 to P37
P40 to P47
V
DDL
SPV
DD
SPV
SS
SG
SPP
SPM
AOUT
SPIN
AV
DD
AV
SS
V
REF
AIN0 to AIN2
MOP0_l1
MOP0_l2
MOP0_O
MOP1_l1
MOP1_l2
MOP1_O
MOP2_l1
MOP2_l2
MOP2_O
TBC
POWER
INT
2
INT
1
VOICECNT
INT
WDT
8bit Timer
×2
INT
1
12bit-ADC
OP-AMP0
OP-AMP1
OP-AMP2
Figure 1 Block Diagram of ML610Q346
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FEDL610Q346DIGEST-01
ML610Q346/346
Figure 2 is a block diagram of the ML610346.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding
port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
（Mask）
128Kbyte
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
OSC0
OSC1
LSCLK*
OUTCLK*
RESET &
TEST
Data-bus
INT
1
SSIO
SCK0*
1
SIN0*
1
SOUT0*
RXD0*
1
TXD0*
1
1
RAM
1024byte
INT
1
UART
OSC
RC32K
INT
4
Interrupt
Controller
INT
9
NMI
P00 to P07
GPIO
P20 to P23
P30 to P37
P40 to P47
V
DDL
V
DDL
SPV
DD
SPV
SS
SG
SPP
SPM
AOUT
SPIN
AV
DD
AV
SS
V
REF
AIN0 to AIN2
MOP0_l1
MOP0_l2
MOP0_O
MOP1_l1
MOP1_l2
MOP1_O
MOP2_l1
MOP2_l2
MOP2_O
TBC
POWER
INT
2
INT
1
VOICECNT
INT
WDT
8bit Timer
×2
INT
1
12bit-ADC
OP-AMP0
OP-AMP1
OP-AMP2
Figure 2
Block Diagram of ML610346
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以拆会友