FEDL610Q409-02
Issue Date: Jul.12, 2011
ML610Q407/ML610Q408/ML61Q0
409
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
ML610Q407/ML610Q408/ML610Q409 is a high-performance 8-bit CMOS microcontroller into which peripheral circuits, such
as synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around
LAPIS Semiconductor-original 8-bit CPU nX-U8/100. ML610Q407/ML610Q408/ML610Q409 operates in both high/low-speed
mode and power-saving mode, it is most suitable for battery operated products.
The short TAT are entertained by offering MTP version ML610Q407(P)/ML610Q408(P)/ML610Q409(P). ML610Q407P/
ML610Q408P/ML610Q409P support industrial temperature -40C to +85C, are added to the product lineup.
FEATURES
CPU
8-bit RISC CPU (CPU name: nX-U8/100)
Instruction system: 16-bit instructions
Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
On-Chip debug function (MTP version only)
Minimum instruction execution time
30.5
s
(@32.768 kHz system clock)
2s (@500kHz system clock)
0.5s(@2MHz system clock)
Internal memory
Internal 16KByte Flash ROM (8K16 bits) (including unusable
1K
Byte TEST area)
Internal 1KByte Data RAM (10248 bits)
Interrupt controller
1 non-maskable interrupt sources
Internal source: 1 (Watch dog timer)
27 maskable interrupt sources
Internal sources: 14 (SSIO0, SSIO1, Timer0, Timer1, Timer2, Timer3, UART0, Melody0, RC-A/D converter, PWM0,
TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz)
External sources: 13 (P00, P01, P02, P03, P04, P50, P51, P52, P53, P54, P55, P56, P57)
(One interrupt request is generated from P50 to P57 interrupt sources.)
Time base counter
Low-speed time base counter
1
channel
Frequency compensation (Compensation range: Approx.
488ppm
to +488ppm. Compensation accuracy: Approx.
0.48ppm)
High-speed time base counter
1
channel
Watchdog timer
Non-maskable interrupt and reset
Free running
Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
Timers
8 bits
4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
FEDL610Q409-01
LAPIS Semiconductor
ML610Q407/ML610Q408/ML610Q409
Capture
Time base capture
2 channels (4096 Hz to 32 Hz)
PWM
Resolution 16 bits
1 channel
Synchronous serial port
Master/slave selectable
2 channel
LSB first/MSB first selectable
8-bit length/16-bit length selectable
UART
Half-Duplex Communication
TXD/RXD
1 channel
Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
Positive logic/negative logic selectable
Built-in baud rate generator
Melody driver
Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
Tone length: 63 types
Tempo:
15 types
Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
RC oscillation type A/D converter
16-bit counter
Time division
2 channels
General-purpose ports
Input-only port
5 channels (including secondary functions)
Output-only port
ML610Q407:
12 channels (including secondary functions)
ML610Q408:
8 channels (including secondary functions)
ML610Q409:
4 channels (including secondary functions)
Input/output port
22 channels (including secondary functions)
LCD driver
The number of segments
ML610Q407: 145 dots max. (29seg5com, 30seg4com, 31seg3com, and 32seg2com selectable)
ML610Q408: 165 dots max. (33seg5com, 34seg4com, 35seg3com, and 36seg2com selectable)
ML610Q409: 185 dots max. (37seg5com, 38seg4com, 39seg3com, and 40seg2com selectable)
1/1 to 1/5 duty
1/2, 1/3 bias (built-in bias generation circuit)
Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz
Bias voltage multiplying clock selectable (8 types)
LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
Programmable display allocation function
Reset
Reset through the RESET_N pin
Power-on reset generation when powered on
Reset when oscillation stop of the low-speed clock is detected
Reset by the watchdog timer (WDT) overflow
Clock
Low-speed clock: Crystal oscillation (32.768 kHz)
(This LSI can not guarantee the operation withoug low-speed crystal oscillation clock)
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FEDL610Q409-01
LAPIS Semiconductor
ML610Q407/ML610Q408/ML610Q409
High-speed clock: Built-in RC oscillation (500 kHz, 2MHz)
Power management
HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
High-speed Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the
oscillation clock)
Block Control Function: Resets and completely turns circuits of unused peripherals off.
Shipment
Chip
ML610Q407-½½½WA
ML610Q408-½½½WA
ML610Q409-½½½WA
ML610Q407D-½½½WA
ML610Q408D-½½½WA
ML610Q409D-½½½WA
ML610Q407P-½½½WA
ML610Q408P-½½½WA
ML610Q409P-½½½WA
ML610Q407PD-½½½WA
ML610Q408PD-½½½WA
ML610Q409PD-½½½WA
100-pin plastic TQFP
ML610Q407-½½½TBZ03A
ML610Q408-½½½TBZ03A
ML610Q409-½½½TBZ03A
ML610Q407D-½½½TBZ03A
ML610Q408D-½½½TBZ03A
ML610Q409D-½½½TBZ03A
ML610Q407P-½½½TBZ03A
ML610Q408P-½½½TBZ03A
ML610Q409P-½½½TBZ03A
ML610Q407PD-½½½TBZ03A
ML610Q408PD-½½½TBZ03A
ML610Q409PD-½½½TBZ03A
xxx: ROM code number (xxx is NNN for blank product)
Q: MTP version
P: Wide range temperature version
D: LCD 1/2 bias waveform alternative version (D version, See the LCD driver section of the user’s manual in detail)
WA: Chip
TBZ03A: TQFP
Guaranteed operating range
Operating temperature:
20C
to +70C (P version:
C
to +85C)
Operating voltage: V
DD
= 1.25V to 3.6V
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FEDL610Q409-01
LAPIS Semiconductor
ML610Q407/ML610Q408/ML610Q409
BLOCK DIAGRAM
ML610Q407/ML610Q408/ML610Q409 Block Diagram
Figure 1 show the block diagram of the ML610Q407/ML610Q408/ML610Q409.
“*” indicates the secondary function of each port.
(*1)
“ ”: 29seg×5com, 30seg×4com, 31seg×3com, and 32seg×2com selectable
“
(*2)
”: 33seg×5com, 34seg×4com, 35seg×3com, and 36seg×2com selectable
“
(*3)
”: 37seg×5com, 38seg×4com, 39seg×3com, and 40seg×2com selectable
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
Data-bus
RAM
1Kbyte
Interrupt
Controller
XT0
XT1
OSC
LSCLK*
OUTCLK*
INT
1
INT
4
Power
INT
1
Capture
×2
INT
4
8bit Timer
×4
INT
1
INT
6
INT
1
UART
TBC
INT
1
PWM
PWM0*
RXD0*
TXD0*
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(MTP)
16Kbyte
V
PP
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST0
TEST1_N
RESET &
TEST
INT
2
SSIO
×2
SCK0*
SIN0*
SOUT0*
SCK1*
SIN1*
SOUT1*
WDT
V
DDL
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
Melody
MD0*
RC-ADC
×2
GPIO
P00 to P04
P20 to P22, P24
P30 to P35
P40 to P47
P50 to P57
P60 to P67 (ML610Q407)
P60 to P63 (ML610Q408)
Display
Allocation
RAM
Display
register
320bit
LCD
Driver
LCD
BIAS
COM0 to COM4
SEG0 to SEG31 (ML610Q407)
(*1)
SEG0 to SEG35 (ML610Q408)
(*2)
SEG0 to SEG39 (ML610Q409)
(*3)
V
L1
, V
L2
, V
L3
C1, C2
(*1)(*2)(*3)
Figure 1 ML610Q407/ML610Q408/ML610Q409 Block Diagram
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FEDL610Q409-01
LAPIS Semiconductor
ML610Q407/ML610Q408/ML610Q409
PIN CONFIGURATION
ML610Q407 TQFP100 Pin Layout
(NC)
V
SS
P20
P21
P22
P24
P00
P01
P02
P03
P04
P30
P31
P34
P32
P33
P35
P57
P56
P55
P54
P53
V
PP
(NC)
(NC)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(NC)
(NC)
P60
P61
P62
P63
P64
P65
P66
P67
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
(NC)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
(NC)
(NC)
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
(NC)
(NC)
P52
P51
P50
P40
P41
P42
P43
P44
P45
P46
P47
V
DD
V
SS
V
DDL
(NC
XT0
XT1
RESET_N
TEST0
TEST1_N
V
L1
V
L2
V
L3
(NC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Note:
The assignment of the P30 to P35 are not in order.
Figure 2 ML610Q407 TQFP100 Pin Configuration
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