FEDL610Q476-01
Issue Date Jan. 11, 2013
ML610Q474/ML610Q475/ML610Q476
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as the UART, melody driver, Analog compartor, and LCD driver.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash
memory incorporated into this MTP version implements the mask ROM-equivalent low-voltage operation (1.25V or higher)
and low-power consumption (typically 4.5uA at low-speed operation), enabling volume production by the MTP version.
FEATURES
•
CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- On-Chip debug function
- Minimum instruction execution time
30.5
μs
(@ 32.768 kHz system clock)
2
μs
(@ 500 kHz system clock)
0.5
μs
(@ 2 MHz system clock)
•
Internal memory
- Internal 16KByte flash memory (8K x 16 bits) (including unusable 1K Byte TEST area)
- Internal 1KByte RAM (1024 x 8 bits)
•
Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 22 maskable interrupt sources:
Internal source: 12 (Timer0, Timer1, Timer 2, Timer 3, Timer C, Timer D, UART0, TBC128Hz, TBC32Hz, TBC16Hz,
TBC2Hz, Analog Comparator)
External source: 10 (P00, P01, P02, P03, P50, P51, P52, P53, P54, P56)
(One interrupt request is generated from P50 to P54, P56 interrupt sources.)
•
Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
•
Watchdog timer
- Non-maskable interrupt and reset
- Free running
- Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
FEDL610Q476-01
ML610Q474/ML610Q475/ML610Q476
•
Timers
- 8 bits x 6 channels [also available is 16-bit x 3 configuration (using Timers 0-1, 2-3, or C-D) ]
- Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only)
- The timer C and timer D are controlled by the external trigger.
- The timer C and timer D are used for the one-shot timer mode.
•
Capture
- Time base capture x 2 channels (4096 Hz to 32 Hz)
•
UART
- TXD/RXD × 1 channel
- Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
- Positive logic/negative logic selectable
- Built-in baud rate generator
•
Melody driver
- Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
- Tone length: 63 types
- Tempo: 15 types
- Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
•
Analog Comparator
- Operating voltage:
V
DD
=1.8V∼3.6V
- Common mode input voltage:
0.2V∼VDD−0.2V
- Input offset voltage:
30mV(max)
- Interrupt allow edge selection and sampling selection
- The RC discharged type A/D convertor is configured with the timers C and D.
- The temperature measurement function using built-in temperature sensor.
Temperature measurement range: -20°C to +70°C
- The reference voltage can be switched between CMPP0, CMPM0, temperature sensor and the internal 0.7V voltage source.
•
General-purpose ports
- Input-only port: 4 channels (including secondary functions)
- Output-only port
ML610Q474: 10 channels (including secondary functions)
ML610Q475: 6 channels (including secondary functions)
ML610Q476: 2 channels (including secondary functions)
- Input/output port: 10 channels (including secondary functions)
•
LCD driver
- Number of segments
ML610Q474: Up to 135 dots (select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3
commons, and 30 segments x 2 commons)
ML610Q475: Up to 155 dots (select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3
commons, and 34 segments x 2 commons)
ML610Q476: Up to 175 dots (select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3
commons, and 38 segments x 2 commons)
- 1/1 to 1/5 duty
- 1/2 or 1/3 bias (built-in bias generation circuit)
- Frame frequency selectable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
- Bias voltage multiplying clock selectable (8 types)
- LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
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FEDL610Q476-01
ML610Q474/ML610Q475/ML610Q476
•
Reset
- Reset through the RESET_N pin
- Power-on reset generation when powered on
- Reset by the watchdog timer (WDT) overflow
- Reset by the low-speed oscillation stop detection (Available by a mask option)
•
Clock
- Low-speed clock (Operation of this LSI is not guaranteed under a condition with no supply of low-speed crystal oscillation
clock)
Crystal oscillation (32.768 kHz)
- High-speed clock
Built-in RC oscillation (500 kHz, 2 MHz)
•
Power management
- HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states)
- STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
- High-speed clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
- Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and
stops clock)
- When LSCLK is selected for system clock, the power consumption can be reduced by using halver circuit.
•
Shipment
−
Chip (Die)
ML610Q474-xxxWA
ML610Q475-xxxWA
ML610Q476-xxxWA
−
80-pin plastic TQFP
ML610Q474-xxxTBZ0ARL
ML610Q475-xxxTBZ0ARL
ML610Q476-xxxTBZ0ARL
xxx: ROM code number (xxx of the blank product is NNN)
Q: MTP version
WA: Chip (Die)
TBZ0ARL: TQFP
•
Guaranteed Operation Range
−
Operating temperature: -20°C to +70°C
−
Operating voltage: V
DD
= 1.25V to 3.6V (2.4V to 3.6V used halver circuit)
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FEDL610Q476-01
ML610Q474/ML610Q475/ML610Q476
BLOCK DIAGRAM
Block Diagram of ML610Q474/ML610Q475/ML610Q476
CPU (nX-U8/100)
EPSW1−3
PSW
Timing
Controller
GREG
0−15
ALU
Instruction
Decoder
ELR1−3
LR
EA
SP
Instruction
Register
Data-bus
V
SS
RESET_N
TEST0
RESET
&
TEST
RAM
1K byte
BUS
Controller
ECSR1−3
DSR/CSR
PC
Program
Memory
(Flash)
16Kbyte
V
PP
On-Chip
ICE
XT0
XT1
LSCLK*
V
DD
V
HF
V
DDL
V
DDX
CH1, CH2
OSC
INT
1
Power
INT
4
Interrupt
Controller
INT
1
UART
RXD0*
TXD0*
WDT
INT
1
TBC
Melody/
Buzzer
MD0*
Capture
×2
INT
6
INT
1
CMPP0*
CMPM0*
Analog
Comparator
8bit Timer
×6
INT
5
P00 to P03
P20, P21
GPIO
P42 to P45
P50 to P54, P56
P60 to P67 (ML610Q474)
P60 to P63 (ML610Q475)
COM0 to COM4 (*1)(*2)(*3)
SEG0 to SEG29 (ML610Q474) (*1)
SEG0 to SEG33 (ML610Q475) (*2)
SEG0 to SEG37 (ML610Q476) (*3)
V
L1
, V
L2
, V
L3
C1, C2
LCD
Driver
Display
register
190bit
LCD
BIAS
function or Tertiary function
(*1) Select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3 commons, and 30
segments x 2 commons with the register
(*2) Select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3 commons, and 34
segments x 2 commons with the register
(*3) Select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3 commons, and 38
segments x 2 commons with the register
Figure 1 ML610Q474/ML610Q475/ML610Q476 Block Diagram
*
Secondary
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FEDL610Q476-01
ML610Q474/ML610Q475/ML610Q476
PACKAGE PIN/CHIP PAD LAYOUT
ML610Q474 80pin TQFP Package Pin Layout
(NC)
P67
P66
P65
P64
P63
P62
P61
P60
P53
P52
P51
P50
P42
P43
V
SS
P20
P21
V
PP
(NC)
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(NC)
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
(NC)
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
V
L3
V
L2
V
L1
C2
C1
(NC)
(NC): No Connection
Figure 2 ML610Q474 80pin TQFP Package Pin Layout
(NC)
P00
P01
P02
P03
P56
P54
P44
P45
V
DD
V
SS
V
DDL
CH1
CH2
V
HF
XT0
XT1
V
DDX
RESET_N
TEST0
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