FEDL62Q1300-02
Issue Date: Sep 27, 2019
ML62Q1300 Group
16-bit micro controller
GENERAL DESCRIPTION
ML62Q1300 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the
multiplier/divider, CRC operator, DMA controller, clock generator, timer, UART, synchronous serial port, I
2
C bus interface unit,
buzzer, Voltage Level Supervisor(VLS), successive approximation type A/D converter, D/A converter , analog comparator, safety
function(IEC60730/60335 Class B) and etc.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1300 Group has five packages (16pin - 32pin) and five kinds of memory sizes(16Kbyte - 64Kbyte).
Table 1 ML62Q1300 Group Product List
Program
memory
64Kbyte
48Kbyte
32Kbyte
32Kbyte
24Kbyte
16Kbyte
2Kbyte
4Kbyte
2Kbyte
Data memory
(RAM)
Data Flash
16pin
SSOP16
WQFN16
－
－
－
ML62Q1325
ML62Q1324
ML62Q1323
20pin
TSSOP20
－
－
－
ML62Q1335
ML62Q1334
ML62Q1333
24pin
WQFN24
ML62Q1347
ML62Q1346
ML62Q1345
－
－
－
32pin
TQFP32
WQFN32
ML62Q1367
ML62Q1366
ML62Q1365
－
－
－
FEATURES
•
CPU
−
16-bit RISC CPU (CPU name: nX-U16/100(A35 core))
−
Instruction system: 16-bit length instruction
‒
Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒
On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
‒
ISP (In-System Programming) function built-in
‒
Minimum instruction execution time
30.5 μs (at 32.768
kHz system clock)
62.5ns/41.6ns (at 16 MHz/24MHz system clock)
•
Coprocessor for multiplication and division
−
Multiplication: 16bit × 16bit (operation time 4 cycles)
−
Division: 32bit / 16bit (operation time 8 cycles)
−
Division: 32bit / 32bit (operation time 16 cycles)
−
Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
−
Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
−
Signed-operation and unsigned-operation are available
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FEDL62Q1300-02
•
Operating voltage and temperature
‒
Operating voltage: V
DD
= 1.6 V to 5.5 V (Need 1.8V or higher at the power on)
‒
Operating temperature: -40°C to +105 °C
•
Internal memory
‒
Program Flash memory area
Rewrite count: 100 cycles
Rewrite unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Rewrite temperature: 0°C to +40°C
‒
Data Flash memory area
Rewrite count 10,000 cycles
Rewrite unit: 8bit(1byte)
Erase unit: All area/128byte
Erase/Rewrite temperature: -40°C to +85°C
Back Ground Operation(CPU can work while erasing and rewriting)
This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc.
‒
Data RAM area
Rewrite unit: 8bit/16bit(1byte/2byte)
Parity check function (Parity error reset or interrupt is generatable)
•
Clock
‒
Low-speed clock
Internal low-speed RC oscillation: Approx.32.768 kHz
‒
High-speed clock
PLL oscillation: 24MHz/16MHz is selectable by code option
‒
WDT(Watch Dog Timer) clock
Internal low-speed RC oscillation: Approx. 1kHz
The WDT independent clock or the divided clock of internal low-speed clock is selectable by the code option.
•
Reset
‒
RESET_N pin reset
‒
Reset by power-on detection
‒
Reset by the 2
nd
watchdog timer (WDT) overflow
‒
Reset by WDT counter clear during the clear invalid period
‒
Reset by RAM parity error
‒
Reset by unused ROM access
‒
Reset by voltage level detection (VLS)
‒
The software reset by BRK instruction (reset CPU only)
‒
Reset to the peripheral circuits by Block Reset Control Registers (BRECON 0 to 3)
‒
One-time reset to the all peripheral circuits by Software Reset Control Register (SOFTRCON)
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FEDL62Q1300-02
•
Power management
‒
HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states
‒
HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits working with
low-speed clock remain previous states
‒
STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
‒
STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop. The internal
regulator’s output voltage (V
DDL
) goes down to reduce the current consumption.
‒
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of the
oscillation clock)
‒
Block Control Function: Powers down the circuits of unused function blocks (reset the block or stop supplying the clock)
•
Interrupt controller
−
Non-maskable interrupt source: 1 (Internal sources: WDT)
−
Maskable interrupt sources: max.32
−
Four step interrupt levels
−
External interrupt ports : max. 8
•
Watchdog timer(WDT)
‒
Operating clock is selectable (1kHz WDT independent clock or divided clock of internal 32.768kHz RC oscillation)
‒
Overflow period: 8 types selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2000ms and 8000ms @32.768kHz)
‒
Enabling or disabling the window function is selectable (The clear enable period is 50% or 75% of overflow period)
‒
WDT operation is selectable by code option (Enable or Disable)
‒
Readable WDT counter (WDT counter monitor function)
‒
The first overflow generates the WDT interrupt, and the second overflow generates the WDT reset when the counter clear
enable period is 100% of overflow period.
‒
The first overflow generates the WDT reset when the counter clear enable period is 50% or 75% of overflow period.
‒
The invalid clear reset generated when the WDT counter is cleared out of the WDT counter clear enable period.
•
DMA(Direct Memory Access) controller
−
Channel : 2ch
−
Transfer unit: 8bit/16bit
−
Max. transfer count: 1024 time
−
Transfer type: 2 cycle transfer
−
Transfer mode: Single transfer mode
Fixed address, address increments and address decrements
−
Transfer target: SFR/RAM
SFR/RAM (Transfer from/to Flash is not supported)
−
Transfer request: Serial communication units, A/D, 16-bit timers, Functional timers and External interrupts.
•
Low-speed Time base counter
−
Divide the Low-speed clock(LSCLK) and generate 128Hz to 1Hz internal pulse signals
−
Periodical interrupt
×
3 selectable from 8 frequencies (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz and 1Hz)
−
The time base clock output (1Hz or 2Hz) from general purpose ports (TBCOUT1).
•
Functional timer(FTM)
−
Channel: 4ch
−
Timer one shot mode and repeat mode, Capture mode, PWM mode1 and PWM mode 2(complementary output)
−
Same start/stop is available with different channels
(This function is not available with 16-bit timers)
−
Event trigger (external interrupts, analog comparators, 16-bit timers and Functional timers)
−
Dead time is generatable.
−
Available to specify division ratio of counter clock channel by channel
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FEDL62Q1300-02
•
16-bit timers
−
Channel: Max. 6ch
‒
8-bits timer mode and 16-bit timer mode (1ch 16-bit timer is configurable as 2ch 8-bit timer)
−
Same start/stop is available with different channels
(This function is not available with Functional Timer)
‒
Timer output (toggled by overflow)
−
Available to specify division ratio of counter clock channel by channel
•
Serial communication unit
−
Channel: 2ch
−
Synchronous Serial Port or UART is selectable in each channel
< Synchronous Serial Port >
‒
Master/slave selectable
‒
LSB first/MSB first selectable
‒
8-bit length/16-bit length selectable
< UART >
‒
Full-duplex communication x 1ch(One Full-duplexUART is configurable as two half-duplex UARTs)
‒
5-8 bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
‒
Positive logic/negative logic selectable
‒
LSB first/MSB first selectable
‒
Wide range of communication speed
32.768kHz clock: 1bps to 4,800bps
24MHz clock: 600bps to 3Mbps
16MHz clock: 300bps to 2Mbps
‒
Internal baud rate generator
•
I
2
C bus interface unit (Master/Slave)
‒
Channel: 1ch
‒
Master or Slave mode is selectable
< Master function >
‒
Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒
Handshake (Clock synchronization)
‒
7bit address format (10bit address format is supported)
< Slave function >
‒
Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒
Clock stretch function
‒
7bit address format
•
I
2
C bus interface (Master only)
‒
Channel: 1ch
‒
Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒
Handshake (Clock synchronization)
‒
7bit address format (10bit address format is supported)
•
General-purpose ports (GPIO)
‒
I/O port: Max. 28 (Including one pin for on-chip debug and pins for other shared functions)
‒
External interrupt function
×
8
‒
LED driver port : Max. 27
‒
Carrier frequency output function (used for IR communication)
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FEDL62Q1300-02
•
Successive approximation type A/D converter
‒
Channel: Max.8ch
‒
Resolution: 10bit
‒
Conversion time: Selectable 2.25μs (min) /channel (When the conversion clock is 8MHz)
‒
V
DD
pin input voltage / Internal reference voltage(Approx. 1.55V) / External reference voltage (V
REF
pin) are selectable
‒
Scan function (repeat conversion)
‒
One result register for each channel
‒
Interrupt by threshold of conversion result
‒
Temperature sensor for low-speed RC oscillation adjustment
•
Voltage level supervisor (VLS)
‒
Accuracy: ±4%
‒
Threshold voltage: 12 values selectable (1.85V ~ 4.00V)
‒
Voltage level detection reset (VLS reset)
‒
Voltage level detection interrupt (VLS0 interrupt)
•
Analog comparator
‒
Channel: 1ch
‒
Interrupts allow edge selection and sampling selection
‒
An external or an internal reference voltage(0.8V) is selectable
•
D/A converter
‒
Channel: Max 1ch
‒
Resolution: 8bit
‒
Output impedance: 6k ohm(Typ.)
‒
R-2R ladder method
•
Buzzer
‒
4 buzzer mode (Repeat sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
‒
8frequencies (4.096kHz to 293Hz)
‒
15 step duty (1/16 to 15/16)
‒
Selectable the logic of buzzer output pin (Positive or Negative logic)
•
CRC(Cyclic Redundancy Check) operation function
‒
Generation equation: X
16
+X
12
+X
5
+1
‒
LSB first or MSB first is selectable
‒
Automatic CRC mode: Automatic CRC calculation with data of program memory in HALT mode
•
Safety Function(IEC60730/60335 Class B)
‒
RAM/SFR guard
‒
Automatic CRC calculation with data of program memory
‒
RAM parity error detection
‒
ROM unused area access reset
‒
Clock mutual check
‒
WDT counter check
‒
Successive approximation type A/D converter test
‒
UART test
‒
Synchronous serial test
‒
I
2
C test
‒
GPIO test
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