ML62Q1500/1800 Group
16-bit micro controller
Issue Date: Mar 19, 2020
FEDL62Q1500-05
ML62Q1500/1800 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the
multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART,
Synchronous serial port, I
2
C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor(VLS), Successive
approximation type A/D converter, D/A converter , Analog comparator, Safety function(IEC60730/60335 Class B) and so on.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1500/1800 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte).
Table 1 ML62Q1500/1800 Group Product List
Program
memory
512Kbyte
384Kbyte
256Kbyte
192Kbyte
160Kbyte
128Kbyte
96Kbyte
64Kbyte
48Kbyte
32Kbyte
8Kbyte
16Kbyte
8Kbyte
16Kbyte
8Kbyte
4Kbyte
16Kbyte
Data memory
(RAM)
32Kbyte
Data Flash
8Kbyte
48pin
TQFP48
－
－
－
－
－
－
ML62Q1534
－
ML62Q1533
ML62Q1532
ML62Q1531
ML62Q1530
52pin
TQFP52
－
－
－
－
－
－
ML62Q1544
－
ML62Q1543
ML62Q1542
ML62Q1541
ML62Q1540
64pin
QFP64
TQFP64
ML62Q1859
ML62Q1858
ML62Q1557
ML62Q1556
ML62Q1555
－
ML62Q1554
－
ML62Q1553
ML62Q1552
ML62Q1551
ML62Q1550
80pin
QFP80
ML62Q1869
ML62Q1868
ML62Q1567
ML62Q1566
ML62Q1565
ML62Q1564
－
ML62Q1563
－
－
－
－
100pin
QFP100
TQFP100
ML62Q1879
ML62Q1878
ML62Q1577
ML62Q1576
ML62Q1575
ML62Q1574
－
ML62Q1573
－
－
－
－
GENERAL DESCRIPTION
FEATURES
•
CPU
−
16-bit RISC CPU: nX-U16/100(A35 core)
−
Instruction system: 16-bit length instructions
‒
Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒
Built-in On-chip debug function
‒
Built-in ISP (In-System Programming) function
‒
Minimum instruction execution time
Approximately
30.5 μs (at 32.768
kHz system clock)
Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)
1/70
FEDL62Q1500-05
•
Coprocessor for multiplication and division
−
Multiplication
: 16bit × 16bit (operation time : 4 cycles)
−
Division
: 32bit
÷
16bit (operation time : 8 cycles)
−
Division
: 32bit
÷
32bit (operation time : 16 cycles)
−
Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)
−
Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)
−
Signed or Unsigned is selectable
•
Operating voltage and temperature
‒
Operating voltage: V
DD
= 1.6 to 5.5 V (V
DD
should be 1.8V or over at Power-on)
‒
Operating temperature: -40 °C to +105 °C
•
Internal memory
‒
Program memory area
Rewrite count: 100 cycles
Write unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Write temperature: 0
°C
to +40
°C
‒
Data Flash memory area
Rewrite count 10,000 cycles
Write unit: 8bit(1byte)
Erase unit: all area/128byte
Erase/Write temperature: -40
°C
to +85
°C
Back Ground Operation(CPU can work while erasing and rewriting)
This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc.
Super Flash® is a registered trademark of Silicon Storage Technology, Inc.
‒
Data RAM area
Rewrite unit: 8bit/16bit (1byte/2byte)
Parity check function is available (interrupt / reset are generatable at Parity error)
•
Clock Generation Circuit
‒
Low-speed clock (LSCLK)
Internal low-speed RC oscillation: Approximately 32.768 kHz
External low-speed clock input: Approximately 32.768 kHz
External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable
3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption)
⋅
Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins
⋅
Normal mode: Normal oscillation allowance and current consumption
⋅
Low current consumption mode: Smallest oscillation allowance to make lower current consumption
‒
High-speed clock (HSCLK)
PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option
‒
Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz)
•
Reset
‒
Reset by reset input pin
‒
Reset by Power-On Reset
‒
Reset by WDT overflow
‒
Reset by WDT invalid clear
‒
Reset by RAM parity error
‒
Reset by unused ROM area access (instruction access)
‒
Reset by voltage level supervisor (VLS)
‒
Software reset by BRK instruction (reset CPU only)
‒
Reset the peripherals individually
‒
Collective reset to the all control pins and peripheral circuits
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FEDL62Q1500-05
•
Power management
‒
HALT mode: CPU stops executing instruction, peripheral circuits continue working
‒
HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits continue
working with low-speed clock
‒
STOP mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed
oscillation stop.
‒
STOP-D mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed
oscillation stop. The internal logic voltage (V
DDL
) goes down to reduce the current consumption (RAM data is retained).
‒
Clock gear: High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK)
‒
Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock)
•
Interrupt controller
−
External interrupt ports : max 12
−
Non-maskable interrupt source: 1 (Internal source: WDT)
−
Maskable interrupt sources: max.51
−
Four step interrupt levels
•
Watchdog timer(WDT)
‒
Selectable Operating clock : select RC1K or LSCLK by code option
‒
Overflow period: 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s)
‒
Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period)
‒
Selectable WDT operation : select Enable or Disable by code option
‒
Readable WDT counter : WDT counter monitor function
•
DMA(Direct Memory Access) controller
−
Channel: 2channel
−
Transfer unit: 8bit/16bit
−
Transfer count: 1 to 1024
−
Transfer cycle: 2 cycle transfer
−
Transfer address: Fixed addressing mode, inclement addressing mode , and decrement addressing mode
−
Transfer target: Special Function Register (SFR)/RAM
SFR/RAM (Transfer from/to Flash is not supported)
−
Transfer request: External pins, Serial communication unit, Successive approximation type A/D converter, 16bit timer,
and Functional timer
•
Low-speed Time base counter
−
Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK)
−
Selectable 3 interrupts from eight frequency internal pulse signals
−
1Hz or 2Hz output from general purpose port
−
Built-in Frequency adjust function : Adjust range: Approximately -488ppm to +488ppm, adjust resolution:
Approximately 0.119ppm
•
Simplified RTC
−
Channel: 1channel
−
Count by a unit for one second from "00 min. 00 sec" to "59 min. 59 sec"
−
Selectable Periodical interrupt request from four periods (0.5s, 1s, 30s or 60s)
−
Built-in minute and second writing error protraction function
3/70
FEDL62Q1500-05
•
Functional timer
−
Channel: Max. 8 channel
−
Built-in timer, capture, and PWM function by 16 bit counter
−
Built-in Repeat mode, One shot mode is available
−
Two types of PWM output with the same period and different duties, and complementary PWM output with the dead time
−
Monitor input signal duty and the period by capture function
−
Generate periodical interrupts, duty interrupts, and interrupts coincided with set value
−
Counter Start, Stop, Counter clear triggered by an external inputs or Timer
−
Generate Emergency stop and emergency stop interrupt triggered by an external input
−
Same start/stop among different channels of the functional timer
−
Selectable counter clock(external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels
•
16-bit General timers
−
Channel: Max. 8channel
‒
8 bits timer mode and 16-bit timer mode
−
Same start/stop among different channels of 16bit (8bit) timer
‒
Timer output (toggled by overflow)
−
Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels
•
Serial communication unit
−
Synchronous Serial Port (SSIO) mode or UART mode is selectable
−
Channel: Max. 6channel
< Synchronous Serial Port mode>
‒
Selectable from Master and Slave
‒
Selectable from LSB first or MSB first
‒
Selectable 8-bit length or 16-bit length
< UART mode>
‒
Full-duplex communication (One Full-duplex UART is configurable as two half-duplex UARTs)
‒
5 to 8 bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits
‒
Selectable from Positive logic or Negative logic
‒
Selectable from LSB first or MSB first
‒
Configurable wide range communication speed
32.768kHz operation clock : 1 bit/s to 4,800 bit/s
24MHz operation clock : 600 bit/s to 3 Mbit/s
16MHz operation clock : 300 bit/s to 2 Mbit/s
‒
Built-in baud rate generator
•
I
2
C bus unit (Master / Slave)
‒
Selectable from Master mode or Slave mode
‒
Channel: 1 channel
< Master function >
‒
Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒
Handshake (Clock synchronization)
‒
7bit address format (10bit address format is supported)
< Slave function >
‒
Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒
Clock stretch function
‒
7bit address format
•
I
2
C bus Master
‒
Channel: 2channel
‒
Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒
Handshake (Clock synchronization)
‒
7bit address format (10bit address format is supported)
4/70
FEDL62Q1500-05
•
General-purpose ports (GPIO)
‒
I/O port: Max. 92 (Including one pin for on-chip debug and pins for other shared functions)
‒
Input port: Max. 2(Including a shared function)
‒
External interrupt port: Max. 12
‒
LED driver port : Max. 91
‒
Carrier frequency output function (used for IR communication)
•
Successive approximation type A/D converter (SA-ADC)
‒
Channel: Max.16channel
‒
Resolution: 10bit
‒
Conversion time: Min. 2.25μs /channel (When the conversion clock speed is 8MHz)
‒
Reference voltages are selectable
(V
DD
pin / Internal reference voltage(V
REFI
= Approximately 1.55V) / External reference voltage (V
REF
pin))
‒
Selected channel repeat conversion
‒
Dedicated result register for each channel
‒
Interrupt determining by upper limit or lower limit threshold of conversion result
•
Voltage Level Supervisor (VLS)
‒
Accuracy: ±4%
‒
Threshold voltage: 12 selectable (from 1.85V to 4.00V)
‒
Functional Voltage level detection reset (VLS reset)
‒
Functional Voltage level detection interrupt (VLS0 interrupt)
•
Analog comparator
‒
Channel: Max. 2 channel
‒
Selectable interrupt from the comparator output (rising edge or falling edge)
‒
Selectable from sampling or without sampling
‒
Comparable with external 2 inputs
‒
Comparable with external input and internal reference voltage (0.8V)
•
D/A converter
‒
Channel: Max. 2 channel
‒
Resolution: 8bit
‒
Output impedance: 6k ohm (Typ.)
‒
R-2R ladder type
•
Buzzer
‒
4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
‒
8frequencies (4.096kHz to 293Hz)
‒
15 step duty (1/16 to 15/16)
‒
Selectable from positive logic buzzer output or negative logic buzzer output
•
CRC(Cyclic Redundancy Check) generator
‒
Generation equation: X
16
+X
12
+X
5
+1
‒
Selectable from LSB first or MSB first
‒
Built-in Automatic program memory CRC calculation mode in HALT mode
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