Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
Semiconductor
ML670100
OKI’s High-Performance CMOS 32-Bit Single Chip Microcontroller
Version 2
Aug., 1999
GENERAL DESCRIPTION
The ML670100 is a high-performance 32-bit microcontroller combining a RISC based, 32-bit CPU core -
the ARM7TDMI
TM
- with memory and such peripheral circuits as timers, serial ports, and analog-to-
digital converter. This combination of 32-bit data processing, built-in memory, and on-chip peripherals
make it ideal for controlling equipment requiring both high speed and high functionality. An external
memory controller supports direct connection to memory and peripheral devices for adding even more
functionality.
FEATURES
Operating Voltage
2.7 to 3.6V
Operating Frequency 25MHz maximum(3.0 to 3.6V)
On-chip memory
-ROM: 128 kilobytes
-RAM: 4 kilobytes
I/O Function
I/O ports: 8 bits x 9, I/O directions are specified at the bit level
Timer
-Flexible timer (16-bit multi-function timer with six channels)
Choice of operating modes: auto-reload timer, compare output, PWM
and capture
-Time base counter with WDT function
Serial Port
-One asynchronous serial port (UART) with baud rate generator
-Two clock synchronous serial port
A-to-D Converter
-8-bit resolution A-to-D converter with eight analog input ports
Interrupt
-Support for 28 interrupt sources: 9 external and 19 internal
Controller
-Choice of eight priority levels for each source
External Memory
-Direct connection to ROM, SRAM, DRAM and peripheral devices
Controller
-Support for four banks: two for ROM, SRAM and I/O devices plus two for
DRAM
-User-configurable bus width (8/16 bits) and wait control and other
parameters for accessing memory and external devices
Clock Generator
-Built-in crystal oscillation circuit and PLL
-Choice of divider ratio (1/1, 1/2, 1/4) for adjusting operating clock frequency
to match the load of processing
Package
144-pin LQFP ( LQFP144-P-2020-0.50-K)
ARM POWERED logo is the registered trademark of ARM Limited. ARM7TDMI is the trademark of ARM Limited.
The Information contained herein can change without notice owing to product and/or technical i
mprovement.
The signal name of negative logic is being changed to nXXX from XXX in this data sheet.
1 / 27
Semiconductor
BLOCK DIAGRAM
ML670100
TDI*
TDO*
nTRST*
TMS*
TCK*
DBGEN*
DBGRQ*
DBGACK*
ARM7TDMI
4 kilobytes
of RAM
Core address bus
Core data bus (32b)
nRST
nEA
DBSEL
TEST
VDD
GND
AVDD
AGND
128 kilobytes
of ROM
Internal
Bus
Controller
External Memory
Controller (XMC)
XA23-16*
XA15-1
nLB/XA0
XD15-8*
XD7-0
nCS0
nRD
nWRE/nWRL
nXWAIT*
nCS1*
nHB/nWRH*
nRAS1*
nWH/nCASH*
nRAS0*
nCAS/nCASL*
nWL/nWE*
nBREQ*
nBACK*
Time Base
Generator
(TBG)
TMIN/TMOUT[5:0]*
TMCLK[1:0]*
Interrupt
Controller
(INT)
nEFIQ
nEIR[7:0]*
Flexible
Timer
Peripheral data bus 16b)
Peripheral address bus
Analog-to-digital
Converter
(ADC)
VREF
AI[7:0]
ASI_TXD*
ASI_RXD*
CSI1_TXD*
CSI1_RXD*
CSI1_SCLK*
CSI0_TXD*
CSI0_RXD*
CSI0_SCLK*
Asynchronous
Serial Interface
(ASI)
Clock
Synchronous
Interface
(CSI0 and CSI1)
Clock
Control
OSC0
OSC1
CLKOUT
FSEL
PLLEN
VCOM
I/O Ports
PIO8[7:0]
PIO7[7:0]
PIO6[7:0]
PIO5[7:0]
PIO4[7:0]
PIO3[7:0]
PIO2[7:0]
PIO1[7:0]
Asterisks indicate signals that aresecondary functions of I/O ports.
Brackets indicate bit ranges.
2 / 27
PIO0[7:0]
Semiconductor
PIN CONFIGURATION (TOP VIEW)
ML670100
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PIO3[4]/nEIR[4]
PIO3[3]/nEIR[3]
PIO3[2]/nEIR[2]
PIO3[1]/nEIR[1]
PIO3[0]/nEIR[0]
VDD
GND
PIO2[7]/nXWAIT
PIO2[6]/nCS1
PIO2[5]/nHB/nWRH
PIO2[4]/nRAS1
PIO2[3]/nWH/nCASH
PIO2[2]/nRAS0
PIO2[1]/nCAS/nCASL
PIO2[0]/nWL/nWE
VDD
GND
nWRE/nWRL
nRD
nCS0
PIO1[7]/XD15
PIO1[6]/XD14
PIO1[5]/XD13
PIO1[4]/XD12
PIO1[3]/XD11
PIO1[2]/XD10
PIO1[1]/XD9
PIO1[0]/XD8
VDD
GND
XD7
XD6
XD5
XD4
XD3
XD2
PIO3[5]/nEIR[5]
PIO3[6]/nEIR[6]
PIO3[7]/nEIR[7]
GND
PIO4[0]/TMIN[0]/TMOUT[0]
PIO4[1]/TMIN[1]/TMOUT[1]
PIO4[2]/TMIN[2]/TMOUT[2]
PIO4[3]/TMIN[3]/TMOUT[3]
PIO4[4]/TMIN[4]/TMOUT[4]
PIO4[5]/TMIN[5]/TMOUT[5]
PIO4[6]/TMCLK[0]
PIO4[7]/TMCLK[1]
GND
VDD
PIO5[0]/CSI0_SCLK
PIO5[1]/CSI0_RXD
PIO5[2]/CSI0_TXD
PIO5[3]/CSI1_SCLK
PIO5[4]/CSI1_RXD
PIO5[5]/CSI1_TXD
PIO5[6]/ASI_RXD
PIO5[5]/ASI_TXD
CLKOUT
GND
OSC0
OSC1
VDD
VCOM
FSEL
PLLEN
nRST
GND
AGND
AI[7]
AI[6]
AI[5]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Top View
INDEX
MARK
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
XD1
XD0
VDD
GND
nEA
nEFIQ
PIO0[7]/XA23
PIO0[6]/XA22
PIO0[5]/XA21
PIO0[4]/XA20
PIO0[3]/XA19
PIO0[2]/XA18
PIO0[1]/XA17
PIO0[0]/XA16
VDD
GND
XA15
XA14
XA13
XA12
XA11
XA10
XA9
XA8
VDD
GND
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA0/nLB
VDD
GND
AI[4]
AI[3]
AI[2]
AI[1]
AI[0]
VREF
AVDD
VDD
TEST
DBSEL
PIO6[0]
PIO6[1]
PIO6[2]
PIO6[3]
PIO6[4]
PIO6[5]
]
PIO6[6]
]
PIO6[7]
PIO7[0]
PIO7[1]
PIO7[2]
GND
VDD
PIO7[3]
PIO7[4]
PIO7[5]
PIO7[6]/nBREQ
PIO7[7]/nBACK
PIO8[0]/DBGACK
PIO8[1]/DBGRQ
PIO8[2]/DBGEN
PIO8[3]/TCK
PIO8[4]/TMS
PIO8[5]/nTRST
PIO8[6]/TDO
PIO8[7]/TDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3 / 27
Semiconductor
PIN DESCRIPTIONS
Signal
Name
Address XA23 -
bus
XA16
XA15 -
XA0
Data bus XD15 -
XD8
XD7- -XD0
Bus
nCS0
control nCS1
signals
nRD
nWRL
nWRH
Type
I/O Direction Description
Output
Output
ML670100
These are bits 23-16 of the external address bus. They represent
secondary functions for I/O port PIO0[7:0].
These are bits 15 - 0 of the external address bus.
nWRE
nLB
nHB
nRAS0
nRAS1
nCASL
nCASH
nWE
nCAS
nWH
nWL
nXWAIT
Bidirectional These are bits 15-8 of the external data bus. They represent
secondary functions for I/O port PIO1[7:0].
Bidirectional These are bits 7-0 of the external data bus.
Output
This output is the chip select signal for bank 0.
Output
This output is the chip select signal for bank 1. It represents a
secondary function for I/O port PIO2[6].
Output
This output is the read signal for SRAM banks (0 and 1).
Output
This output is the Write Enable Low signal for SRAM banks (0
and 1).
Output
This output is the Write Enable High signal for SRAM banks (0
and 1). It represents a secondary function for I/O port
PIO2[5].
Output
This output is the Write Enable signal for SRAM banks (0 and
1).
Output
This output is the Low Byte Select signal for SRAM banks (0
and 1).
Output
This output is the High Byte Select signal for SRAM banks (0
and 1). It represents a secondary function for I/O port PIO2[5].
Output
This output is the Row Address Strobe signal for bank 2.
It represents a secondary function for I/O port PIO2[2].
Output
This output is the Row Address Strobe signal for banks 3.
It represents a secondary function for I/O port PIO2[4].
Output
This output is the Column Address Strobe Low signal for
DRAM banks (2 and 3). It represents a secondary function for
I/O port PIO2[1].
Output
This output is the Column Address Strobe High signal for
DRAM banks (2 and 3). It represents a secondary function for
I/O port PIO2[3].
Output
This output is the Write Enable signal for DRAM banks (2 and
3). It represents a secondary function for I/O port PIO2[0].
Output
This output is the Column Address Strobe signal for DRAM
banks (2 and 3). It represents a secondary function for I/O port
PIO2[1].
Output
This output is the Write Enable High signal for DRAM banks
(2 and 3). It represents a secondary function for I/O port
PIO2[3].
Output
This output is the Write Enable Low signal for DRAM banks (2
and 3). It represents a secondary function for I/O port PIO2[0].
Input
This input pin controls insertion of wait cycles. It represents a
secondary function for I/O port PIO2[7].
4 / 27
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