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ML670100-XXXTC-K

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Microcontroller
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477KB,共204页
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概述
Microcontroller
器件参数
参数名称
属性值
厂商名称
LAPIS Semiconductor Co Ltd
包装说明
,
Reach Compliance Code
unknown
文档解析
ML670100是一款基于ARM7TDMI核心的高性能32位微控制器,专为需要高速数据处理和高功能集成的应用设计。它采用RISC架构,支持32位ARM和16位THUMB双指令集,优化性能与代码效率。片上集成128KB ROM和4KB RAM,减少外部存储依赖,并内置时钟发生器与PLL,支持频率倍频调整。适用于商业电子设备,如办公自动化和通信系统,提供可靠的嵌入式控制解决方案。 关键组件包括灵活定时器(FTM),提供6通道16位定时功能,支持自动重载、比较输出、PWM和捕获模式;时间基发生器(TBG)内置看门狗定时器,确保系统稳定性;中断控制器管理28个源(9外部+19内部),支持8级优先级处理。此外,I/O端口(8位×9)和模拟输入(8通道)增强连接灵活性。 外部内存控制器支持直接连接ROM、SRAM和DRAM,通过4个bank实现可配置访问参数,适用于扩展存储需求。封装为144-pin LQFP,便于集成到各类设备中,满足工业标准要求,确保高兼容性和易部署性。
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Semiconductor
ML670100
Users’ Manual
Version 1.0 of April, 1999
NOTICE
1.
The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to
is up-to-date.
The outline of action and examples for application circuits described herein have been chosen as
an explanation for the standard action and performance of the product. When planning to use the
product, please ensure that the external conditions are reflected in the actual circuit and assembly
designs.
When designing your product, please use our product below the specified maximum ratings and
within the specified operating ranges including, but not limited to, operating voltage, power
dissipation, and operating temperature.
OKI assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair,
alteration or accident, improper handling, or unusual physical or electrical stress
including, but not limited to, exposure to parameters beyond the specified maximum
ratings or operation outside the specified operating range.
Neither indemnity against nor license of a third party's industrial and intellectual property right,
etc. is granted by us in connection with the use of product and/or the information and drawings
contained herein. No responsibility is assumed by us for any infringement of a third party’s right
which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment for
commercial applications (e.g., office automation, communication equipment, measurement
equipment, consumer electronics, etc.). These products are not authorized for use in any system or
application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or
damage of property, or death or injury to humans. Such applications include, but are not limited
to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including
life support and maintenance.
Certain products in this document may need governmental approval before they can be exported to
particular countries. The purchaser assumes the responsibility of determining the legality of export
of these products and will take appropriate and necessary steps at their own expense for these.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
2.
3.
4.
5.
6.
7.
8.
Copyright 1998 OKI ELECTRIC INDUSTRY CO., LTD.
ARM, Thumb and ARM POWERED logo are the registered trademarks of ARM Ltd.
ARM7TDMI and EmbeddedICE are the trademarks of ARM Ltd.
The signal names of negative logic are being changed to nXXX from XXX in this users manual.
Contents
1
1.1
1.2
1.3
Overview
Features
Block Diagram
Pins
1.3.1
1.3.2
1.3.3
1.3.4
Pin Layout
Pin Functions
Treatment of Unused Pins
Configurations of Pins and I/O ports
1-1
1-2
1-4
1-5
1-5
1-6
1-10
1-11
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
CPU
CPU Operating States
Switching State
Memory Formats
Instruction Length
Data Types
Operating Modes
Registers
2.7.1
2.7.2
2.7.3
2.7.4
The ARM state register set
The THUMB state register set
The relationship between ARM and THUMB state registers
Accessing Hi registers in THUMB state
2-1
2-2
2-2
2-2
2-3
2-3
2-3
2-3
2-4
2-6
2-7
2-7
2-8
2-8
2-8
2-9
2-10
2-10
2-10
2-11
2-11
2-12
2.8
The Program Status Registers
2.8.1
2.8.2
The condition code flags
The control bits
2.9
Exceptions
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
2.9.6
Action on entering an exception
Action on leaving an exception
Exception entry/exit summary
FIQ
IRQ
Software interrupt
i
2.9.7
2.9.8
2.9.9
2.10
Reset
Undefined instruction
Exception vectors
Exception priorities
2-12
2-12
2-13
2-13
3
3.1
CPU Control Functions
Overview
3.1.1
3.1.2
Pins
Control Registers
3-1
3-2
3-2
3-3
3-3
3-3
3-4
3-5
3-6
3-6
3-6
3-7
3-8
3.2
Control Registers
3.2.1
3.2.2
3.2.3
Standby Control Register (SBYCON)
Clock Control Register (CKCON)
Reset Status Register (RSTST)
3.3
System Resets
3.3.1
3.3.2
External Reset Signal (nRST)
Watchdog Timer (WDT) Counter Overflow
3.4
3.5
Clock Signals
Standby Mode
4
4.1
Interrupt Controller
Overview
4.1.1
4.1.2
4.1.3
Block Diagram
Pins
Control Registers
4-1
4-2
4-2
4-4
4-4
4-5
4-5
4-5
4-6
4-6
4-8
4-8
4-8
4-9
4-10
4.2
Interrupt Sources
4.2.1
4.2.2
4.2.3
4.2.4
External Fast Interrupt Requests
External Interrupt Requests
Internal Interrupt Requests
Interrupt Source Mappings
4.3
Control Registers
4.3.1
4.3.2
4.3.3
4.3.4
Interrupt Number Register (INR)
Current Interrupt Level Register (CILR)
Interrupt Request Level Register (IRLR)
External FIQ Control Register (EFIQCON)
ii
4.3.5
4.3.6
4.3.7
4.4
External IRQ Control Register (EIRCON)
Interrupt Request Registers 0 to 3 (IRRn, n=0 - 3)
Interrupt Level Control Registers 0 to 15 (ILCONn, n=0 - 15)
4-11
4-12
4-12
4-14
4-14
4-14
4-20
4-21
Interrupt Processing
4.4.1
4.4.2
External Fast Interrupt Requests
External and Internal Interrupt Requests
4.5
4.6
Sampling Timing for External Interrupt Requests
Interrupt Response Times
5
5.1
I/O Ports
Overview
5.1.1
Control Registers
5-1
5-2
5-4
5-5
5-5
5-5
5-6
5-6
5-9
5-9
5-9
5-9
5.2
Control Registers
5.2.1
5.2.2
5.2.3
5.2.4
Port Output Registers 0 to 8 (POn, n=0 - 8)
Port Input Registers 0 to 8 (PIn, n=0 - 8)
Port Mode Registers 0 to 8 (PMn, n=0 - 8)
Port Function Selection Registers 0 to 5, 7(PFSn, n=0 - 5, 7)
5.3
I/O Port Operation
5.3.1
5.3.2
5.3.3
Configuration after System Reset
Reading from I/O Ports
Writing to I/O Ports
6
6.1
Time Base Generator
Overview
6.1.1
6.1.2
Block Diagram
Control Registers
6-1
6-2
6-2
6-3
6-4
6-4
6-4
6-6
6-6
6-7
6-8
6-8
6.2
Control Registers
6.2.1
6.2.2
Watchdog Timer Control Register (WDTCON)
Time Base Generator Control Register (TBGCON)
6.3
Time Base Generator (TBG) Operation
6.3.1
6.3.2
6.3.3
6.3.4
Time Base Counter (TBC)
Watchdog Timer (WDT)
Time to Overflow
WDT Watchdog Timer Operation
iii
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