PEDL7048-01-01
1
Semiconductor
ML7048-01
3-Channel Single Rail CODEC
This version:
Oct. 2001
Preliminary
GENERAL DESCRIPTION
The ML7048 is a three-channel single rail CMOS CODEC LSI. This device contains filters for A-to-D and D-to-
A conversions of voice signals ranging 300 to 3400 Hz.
The ML7048 is designed for a single power supply and low power applications and contains three-channel A-to-
D and D-to-A converters on a single chip, and achieves a reduced footprint and external component parts.
The ML7048 is best suited for ISDN terminal and digital telephone terminal applications.
FEATURES
• Single 5 V Power Supply Operation
• Using
∆-Σ
ADC and DAC Technique
• Low Power Consumption
3-Channel Operating Mode:
typical: 140 mW max.:174 mW
Power Saving Mode: (PDN = “1”, PDN1 to 3 = “0”) typical: 15 mW max.: 26 mW
Power Down Mode: (PDN = “0”)
typical: 0.05 mW max.: 0.3 mW
• ITU-T Companding Law:
µ-law
• PCM Interface:
3-Channel Independent or 3-Channel Continuous Serial Interface Pin Selectable
• Master Clock:
12.288 MHz or 15.360 MHz Pin Selectable
• Transmission Clocks:
64, 128, 256, 512, 1024, 2048 kHz
96, 192, 384, 768, 1536 kHz
• Adjustable Transmit Gain for Each Channel
• Built-in Reference Voltage Supply
• Differential Analog Output can Directly Drive a 600Ω Transformer.
• Package:
44-pin Plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML7048-01GA)
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PEDL7048-01-01
1
Semiconductor
ML7048-01
BLOCK DIAGRAM
Compressor
Compressor
AIN1–
AIN1+
GSX1
AIN2–
AIN2+
GSX2
AIN3–
AIN3+
GSX3
RC
LPF
∆-Σ
AD
CONV.
BPF
RC
LPF
∆-Σ
AD
CONV.
TCONT
DOUT1
DOUT2
DOUT3
XSYNC
BPF
RC
LPF
∆-Σ
AD
CONV.
BPF
Compressor
BCLK
Expander
RC
LPF
∆-Σ
DA
CONV.
LPF
P/S
AOUT1+
AOUT1–
Expander
RCONT
RSYNC
DIN1
DIN2
DIN3
AOUT2+
RC
LPF
∆-Σ
DA
CONV.
LPF
AOUT2–
Expander
AOUT3+
RC
LPF
∆-Σ
DA
CONV.
LPF
AOUT3–
Power Cont.
&
DLL
&
Clock Gen.
MCKSEL
MCK
PDN
PDN1
PDN2
PDN3
SGC
VDDA
V
DD
AG
DG
SG
Gen.
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PEDL7048-01-01
1
Semiconductor
ML7048-01
PIN CONFIGURATION (TOP VIEW)
42 AOUT1+
41 AOUT1–
44 AIN1–
37 PDN3
36 PDN2
35 PDN1
43 GSX1
AIN1+ 1
VDDA 2
AOUT2– 3
AOUT2+ 4
GSX2 5
AIN2– 6
AG 7
AIN2+ 8
VDDA 9
SGC 10
AIN3+ 11
AIN3– 12
GSX3 13
AOUT3+ 14
AOUT3– 15
AG 16
DG 17
V
DD
18
MCKSEL 19
MCK 20
BCLK 21
P/S 22
34 PDN
33 TEST3
32 DOUT3
31 DOUT2
30 DOUT1
29 DG
28 DIN3
27 DIN2
26 DIN1
25 RSYNC
24 XSYNC
23 TEST2
44-Pin Plastic QFP
39 DG
38 V
DD
40 AG
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PEDL7048-01-01
1
Semiconductor
ML7048-01
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
AIN1+
VDDA
AOUT2–
AOUT2+
GSX2
AIN2–
AG
AIN2+
VDDA
SGC
AIN3+
AIN3–
GSX3
AOUT3+
AOUT3–
AG
DG
V
DD
MCKSEL
MCK
BCLK
P/S
TEST2
XSYNC
RSYNC
DIN1
DIN2
DIN3
DG
DOUT1
DOUT2
DOUT3
TEST3
PDN
PDN1
PDN2
PDN3
V
DD
DG
AG
AOUT1–
AOUT1+
GSX1
AIN1–
Type
I
—
O
O
O
I
—
I
—
O
I
I
O
O
O
—
—
—
I
I
I
I
I
I
I
I
I
I
—
O
O
O
I
I
I
I
I
—
—
—
O
O
O
I
Description
Channel-1 Transmit Amp Non-inverting Input
Analog Power Supply
Channel-2 Receive Amp Inverting Output
Channel-2 Receive Amp Non-inverting Output
Channel-2 Transmit Amp Output
Channel-2 Transmit Amp Inverting Input
Analog Ground
Channel-2 Transmit Amp Non-inverting Input
Analog Power Supply
Analog Signal Ground
Channel-3 Transmit Amp Non-inverting Input
Channel-3 Transmit Amp Inverting Input
Channel-3 Transmit Amp Output
Channel-3 Receive Amp Non-inverting Output
Channel-3 Receive Amp Inverting Output
Analog Ground
Digital Ground
Digital Power Supply
Master Clock Frequency Select Signal
Master Clock
PCM Signal Shift Clock
3-Channel Independent/3-Channel Continuous Serial Interface
Select Signal
Test Control Signal 2
Transmit Sync Signal
Receive Sync Signal
Channel-1 PCM Signal Input
Channel-2 PCM Signal Input
Channel-3 PCM Signal Input
Digital Ground
Channel-1 PCM Signal Output
Channel-2 PCM Signal Output
Channel-3 PCM Signal Output
Test Control Signal 3
Power Down Control Signal
Channel-1 Power Down Control Signal
Channel-2 Power Down Control Signal
Channel-3 Power Down Control Signal
Digital Power Supply
Digital Ground
Analog Ground
Channel-1 Receive Amp Inverting Output
Channel-1 Receive Amp Non-inverting Output
Channel-1 Transmit Amp Output
Channel-1 Transmit Amp Inverting Input
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PEDL7048-01-01
1
Semiconductor
ML7048-01
PIN FUNCTIONAL DESCRIPTION
AIN1+, AIN2+, AIN3+, AIN1–, AIN2–, AIN3–, QSX1, GSX2, GSX3
AIN1+, AIN1– and GSX1 are the transmit inputs and transmit level adjustment pins for Channel 1, AIN2+, AIN2–
and GSX2 are those for Channel 2. AIN3+, and AIN3– and GSX3 are those for Channel 3.
AIN1+, AIN2+ and AIN3+ are non-inverting inputs for the op-amp.
AIN1–, AIN2– and AIN3– are inverting inputs for the op-amp.
GSX1, GX2 and GX3 are the outputs for op-amp.
Do the level adjustment as described below.
If AINn– and AINn+ are not used, connect AINn– to GSXn and AINn+ to SGC.
During power saving and power down modes, GSX1, GSX2, and GSX3 outputs are at a high impedance. During
power down mode in each channel, the GSX output of a channel in power down mode is at a high impedance.
GSXn
Channel n
analog input
R2n
C1n R1n
AINn–
AINn+
Channel n gain
Gain = R2n/R1n
≤
10
R1: Variable
R2
>
20 kΩ
C1n
>
1/(2
×
3.14
×
30
×
R1n)
R1 + R2 < 500 kΩ
SGC
SG
Gen.
AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, AOUT3–
AOUT1+ and AOUT1– are the receive analog output pins for Channel 1, AOUT2+ and AOUT2– are those for
Channel 2, and AOUT3+ and AOUT3– are those for Channel 3.
AOUT1– is the inverting output for AOUT1+, AOUT2– is for AOUT2+, and AOUT3– is for AOUT3+. A load of
600Ω or more can be driven between AOUT1+ and AOUT1–, AOUT2+ and AOUT2–, and AOUT3+ and
AOUT3–. The output signal has an amplitude of 3.4 Vpp above and below the signal ground voltage (SG) when
the digital signal of 3.17 dBm0 is input to DIN1, DIN2, and DIN3.
During power saving and power down modes, the AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, and
AOUT3– outputs are at a high impedance.
During power down mode in each channel, the AOUTn+ and AOUTn– of a channel in power down are at a high
impedance.
SGC
Bypass capacitor pin used to generate the signal ground voltage level.
Connect a 1
µF
capacitor with excellent high frequency characteristics between the SGC pin and the AG pin.
MCK
Master clock input pin. The frequency is 12.288 MHz or 15.360 MHz.
The frequency is switched by MCKSEL. This master clock may be asynchronous with BCLK, RSYNC, and
XSYNC.
MCKSEL
Master clock frequency select signal input pin. Input a 12.288 MHz clock to the MCK pin when MCKSEL is “0”.
Input a 15.360 MHz clock to the MCK pin when MCKSEL is “1”.
PDN
Power down control signal input pin. When PDN is “0”, all circuits are in power down mode.
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