Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
OKI Semiconductor
ML9058
132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
FEDL9058-01
Issue Date:
Sep.
18, 2003
GENERAL DESCRIPTION
The ML9058 is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot
matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU).
Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the
ML9058 makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips.
Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is
possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip,
it is possible to construct a graphic display system with a maximum of 65
×
132 dots. The display can be expanded
further using two chips. However, the ML9058 is not used in a multiple chip configuration when a line reversal
drive is set.
The ML9058 is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of its
features, and is therefore suitable for displays in battery-operated portable equipment.
The ML9058 has 65 common signal outputs and 132 segment signal outputs and one chip can drive a display of up
to 65
×
132 dots.
FEATURES
•
Direct display of the RAM data using the bit map method
Display RAM data “1” ... Dot is displayed
Display RAM data “0” ... Dot is not displayed (during forward display)
•
Display RAM capacity
65
×
132 = 8580 bits
•
LCD Drive circuits
65 common outputs, 132 segment outputs
•
MPU interface: Can select an 8-bit parallel or serial interface
•
Built-in voltage multiplier circuit for the LCD drive power supply
•
Built-in LCD drive voltage adjustment circuit
•
Built-in LCD drive bias generator circuit
•
Can select frame reversal drive or line reversal drive by command
•
Built-in oscillator circuit (Internal RC oscillator/external clock input)
•
A variety of commands
Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page
address, set display start address, etc.
•
Power supply voltage
Logic power supply: V
DD
-V
SS
= 3.7 V to 5.5 V
Voltage multiplier reference voltage: V
IN
-V
SS
= 3.7 V to 5.5 V
(2- to 4-time multiplier available)
LCD Drive voltage: V
BI
-V
SS
= 6.0 to 18 V
•
Package: Gold bump chip (Bump hardness: Low, DV)
: Gold bump chip (Bump hardness: High, CV)
•
This device is not resistant to radiation and light.
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FEDL9058-01
OKI Semiconductor
ML9058
BLOCK DIAGRAM
SEG131
COMS0
Display timing generator circuit
COMS1
COM63
COM0
SEG0
V
DD
V1
V2
V3
V4
V5
V
SS
Common Output state
selection circuit
SEGMENT
Drivers
COMMON
Drivers
VS1–
VS2–
Page address circuit
VC3+
Power supply circuit
VC4+
VC5+
VC6+
V
OUT
V
IN
VR
VRS
IRS
Display data latch circuit
COMS
FRS
FR
CL
DOF
M/S
Display data RAM
65
×
132
Oscillator circuit
Column address circuit
Line address circuit
I/O Buffer
CLS
TEST1
Bus holder
Command decoder
Status
MPU lnterface
DB6(SCL)
WR(R/W)
DB7(SI)
RD(E)
P/
S
CS2
RES
CS1
DB4
DB3
DB1
C86
DB5
DB2
DB0
A0
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FEDL9058-01
OKI Semiconductor
ML9058
ABSOLUTE MAXIMUM RATINGS
V
SS
= 0 V
Parameter
Power supply voltage
Bias voltage
Voltage multiplier output
voltage
Voltage multiplier reference
voltage
Input voltage
Storage temperature range
Symbol
V
DD
V
BI
V
OUT
Condition
Tj = 25°C
Tj = 25°C
Tj = 25°C
2-time multiplication
V
IN
V
I
T
STG
3-time multiplication
4-time multiplication
Tj = 25°C
Chip
Rated value
–0.3 to +6.5
–0.3 to +20
–0.3 to +20
–0.3 to +5.5
–0.3 to +5.5
–0.3 to +5.0
–0.3 to V
DD
+0.3
–55 to +125
V
°C
All inputs
—
V
V
IN
Unit
V
V
V
Applicable pins
V
DD
V1 to V5
V
OUT
Tj:Chip surface temperature
RECOMMENDED OPERATING CONDITIONS
V
SS
= 0 V
Parameter
Power supply voltage
Bias voltage
Voltage multiplier reference
voltage
Voltage multiplier output
voltage
Operating temperature range
Symbol
V
DD
V
BI
V
IN
Condition
—
—
2-time multiplication
3-time multiplication
4-time multiplication
V
OUT
T
JOP
External input
—
Rated value
3.7 to 5.5
6 to 18
3.7 to 5.5
3.7 to 5.5
3.7 to 4.5
6.0 to 18
–40 to +85
V
°C
V
OUT
—
V
V
IN
Unit
V
V
Applicable pins
V
DD
V1 to V5
Note 1:
The electrical characteristics are influenced by COG trace resistance. This LSI always has to
be evaluated before using.
V
OUT
V
IN
V
CC
GND
System (MPU)
V
DD
V
SS
ML9058
V1 to V5
Note 2:
Note 3:
Note 4:
The voltages V
DD
, V1 to V5, and V
OUT
are values taking V
SS
= 0 V as the reference.
The highest bias potential is V1 and the lowest is V
SS
.
Always maintain the relationship V1
≥
V2
≥
V3
≥
V4
≥
V5
≥
V
SS
among these voltages.
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FEDL9058-01
OKI Semiconductor
ML9058
Note 5:
When using an external power supply, follow the procedure for power application.
When applying external power to the V
OUT
pin only, apply V
OUT
after V
DD.
When applying external power to the V1 pin only, apply V1 after V
DD
.
When applying external power to the V1 pin to V5 pin, apply V1 to V5 after V
DD
.
Note that the above (Note 4) must be satisfied including transient state at power application.
Note 6: When using an external power supply, follow the procedure for power removal described
below.
When external power is in use for the V
OUT
pin only, remove V
OUT
after V
DD
.
When external power is in use for the V1 pin only, remove V1 after V
DD
.
When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after V
DD
.
Note that the above (Note 4) must be satisfied including transient state at power removal.
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