QSY-43393
ML9372DVx
Specification
(64-Channel Organic EL Cathode Driver)
Issue Date: Oct. 3, 2005
OKI Semiconductor
ML9372
64-Channel Organic EL Cathode Driver
GENERAL DESCRIPTION
The ML9372 is an organic EL cathode driver LSI with 64 outputs. Since this LSI has an output condition setting
function, which allows setting of all outputs High, all outputs Low, and all outputs High Impedance, the user can
set driving methods suited to the characteristics of an individual organic EL panel. When combined with ML936x,
the organic EL anode driver series, the ML9372 can drive a full-dot panel.
FEATURES
•
•
•
•
•
•
•
•
•
Logic power supply voltage
: 2.7 to 5.5 V
EL drive voltage
: 8.0 to 20 V
Cathode outputs
: 64 outputs
Cathode low output current
: 150 mA (max.)
Cathode high output current : –50 mA (max.)
Cathode low ON-resistance
: 10Ω or less
Cathode high ON-resistance : 100Ω or less
All outputs High, all outputs Low, or all outputs High Impedance can be set as output conditions.
Package
: Gold bump chip (ML9372DVWA)
TCP (ML9372DVVxZ0yy (Vx denotes TCP version; yy is determined by the
direction of the chip in relation to the reel).)
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OKI Semiconductor
ML9372
BLOCK DIAGRAM
OUT1
OUT64
VDISP
GND-D
Cathode driver
VDD
HZ
ALL H
ODD L
EVEN L
TEST
RES
HZ
ALL H
ODD L
EVEN L
TEST
RES
PO1
Output control circuit
PO2
PO63 PO64
DATA I/O
CLK I/O
F/R
GND-L
SIO
CIO
F/R
RES
Shift register
SOI
COI
DATA O/I
CLK O/I
PIN CONFIGURATION (Gold bump chip)
OUT1
OUT2
OUT63 OUT64
GND-D
GND-D
VDISP
VDISP
GND-D
ML9372
GND-D
VDISP
VDISP
GND-L
CLK I/O
ALL H
ODD L
EVEN L
HZ
TEST
RES
VDD
F/R
CLK O/I
GND-L
DATA O/I
DATA I/O
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OKI Semiconductor
ML9372
PIN DESCRIPTION
Symbol
V
DISP
V
DD
GND-D
GND-L
Type
Description
V
DISP
is the cathode driver circuit power supply pin.
V
DD
is the logic circuit power supply pin.
D-GND is a ground pin for cathode driver circuit.
L-GND is a ground pin for logic circuit.
D-GND and L-GND should be connected outside the LSI.
Input pin for register initialization signal. (Pull-down input)
When this pin is set low, the LSI enters the following initial setting states:
• Shift register outputs (PO1 to PO64): all “low”
• All cathode drive signal outputs (OUT1 to OUT64): “high impedance”
Input pin for data transfer direction select signal for shift register. (Pull-down input)
• When this pin is low, data is transferred starting at PO1 toward PO64.
• When this pin is high, data is transferred starting at PO64 toward PO1.
Cathode scan data input-output pin.
When the
F/R
pin is low, this pin is an input pin, and when it is high, this pin is an output
pin.
Cathode scan data input-output pin.
When the
F/R
pin is low, this pin is an output pin, and when it is high, this pin is an input
pin.
Cathode scan data transfer clock input-output pin. (Schmitt trigger input)
When the
F/R
pin is low, this pin is an input pin, and when it is high, this pin is an output
pin.
Cathode scan data transfer clock input-output pin. (Schmitt trigger input)
When the
F/R
pin is low, this pin is an output pin, and when it is high, this pin is an input
pin.
Input pin for cathode drive signal output control signal. (Pull-down input)
When this pin is low, all cathode drive signal outputs (OUT1 to OUT64) are high
impedance.
Input pin for cathode drive signal output control signal. (Schmitt trigger and pull-down
input)
When this pin is high, all cathode drive signal outputs (OUT1 to OUT64) are high.
Input pins for cathode drive signal output control signals. (Schmitt trigger and pull-down
input)
When the ODD L pin is high, all odd number pin outputs are low.
When the EVEN L pin is high, all even number pin outputs are low.
Pin for production tests. Leave this pin open or connect it to L-GND. (Pull-down input)
Cathode drive signal output pin.
—
RES
I
F/R
I
DATA I/O
I/O
DATA O/I
O/I
CLK I/O
I/O
CLK O/I
O/I
HZ
I
ALL H
I
ODD L
EVEN L
TEST
OUT 1 to 64
I
I
O
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OKI Semiconductor
ML9372
FUNCTION TABLE
1. Shift Register Operation during Cathode Scan Data Transfer
Input/Output
CLK
DATA
I/O
I/O
Input
Input
Output
Output
L
H
L
H
Shift Register Parallel Out
CLK
O/I
Output
Input
DATA
O/I
Output
Input
PO1
L
L
L
H
PO2
L
L
PO1n
PO1n
RES
L
F
/R
L
H
PO63
L
L
PO62n
PO62n
PO64
L
L
PO63n
PO63n
L
H
H
Output
Output
Invariable
L
H
L
H
PO2n
PO2n
PO3n
PO3n
PO64n
PO64n
Output
Output
L
H
Invariable
PO1n to PO64n: States of PO1 to PO64 immediately before the clock rises
2. Operation of Output Section
RES
L
HZ
X
L
ALL H
X
X
H
H
H
ALL L
X
X
X
H
L
L
POm
L
X
X
X
H
L
X: Don’t Care
OUTm
High impedanc
e
High impedance
High
Low (weak)
Low (strong)
High
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