MM54HCT109 MM74HCT109 Dual J-K Flip-Flops with Preset and Clear
January 1988
MM54HCT109 MM74HCT109
Dual J-K Flip-Flops with Preset and Clear
General Description
These high speed J-K FLIP-FLOPS utilize advanced silicon-
gate CMOS technology They possess the low power con-
sumption and high noise immunity of standard CMOS inte-
grated circuits along with the ability to drive 10 LS-TTL
loads
Each flip flop has independent J K PRESET CLEAR and
CLOCK inputs and Q and Q outputs These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input
The 54HCT 74HCT logic family is functionally as well as
pin-out compatible with the standard 54LS 74LS logic fami-
ly All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
MM54HCT MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs
Features
Y
Y
Y
Y
Typical propagation delay 20 ns
Low input current 1
mA
maximum
Low quiescent current 40
mA
maximum (74HCT Series)
Output drive capability 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Outputs
Q
Q
u
u
u
u
L
H
L
L
H
H
H
L
H
TOGGLE
Q0
Q0
H
L
Q0
Q0
Order Number MM54HCT109 or MM74HCT109
TL F 5361 – 1
TL F 5361 – 2
C
1995 National Semiconductor Corporation
TL F 5361
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
Operating Conditions
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
V
OUT
)
Operating Temp Range (T
A
)
MM74HCT
MM54HCT
Input Rise or Fall Times
(t
r
t
f
)
Min
45
0
Max
55
V
CC
Units
V
V
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
I
OK
)
DC Output Current per pin (I
OUT
)
DC V
CC
or GND Current per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S O Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
b
0 5 to
a
7 0V
b
1 5 to V
CC
a
1 5V
b
0 5 to V
CC
a
0 5V
g
20 mA
g
25 mA
g
50 mA
b
40
b
55
a
85
a
125
C
C
ns
500
b
65 C to
a
150 C
600 mW
500 mW
260 C
DC Electrical Characteristics
V
CC
e
5V
g
10% (unless otherwise specified)
Symbol
Parameter
Conditions
T
A
e
25 C
Typ
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
V
IN
e
V
IH
or V
IL
l
I
OUT
l
e
20
mA
l
I
OUT
l
e
4 0 mA V
CC
e
4 5V
l
I
OUT
l
e
4 8 mA V
CC
e
5 5V
V
IN
e
V
IH
or V
IL
l
I
OUT
l
e
20
mA
l
I
OUT
l
e
4 0 mA V
CC
e
4 5V
l
I
OUT
l
e
4 8 mA V
CC
e
5 5V
V
IN
e
V
CC
or GND
V
IH
or V
IL
V
IN
e
V
CC
or GND
I
OUT
e
0
mA
V
IN
e
2 4V or 0 5V (Note 4)
Note 2
Unless otherwise specified all voltages are referenced to ground
Note 3
Power Dissipation temperature derating
plastic ‘‘N’’ package
b
12 mW C from 65 C to 85 C ceramic ‘‘J’’ package
b
12 mW C from 100 C to 125 C
Note 4
Measured per pin all other inputs held at V
CC
or GND
74HCT
T
A
eb
40 to 85 C
54HCT
T
A
eb
55 to 125 C
Units
Guaranteed Limits
20
08
20
08
20
08
V
V
V
CC
42
52
0
02
02
V
CC
b
0 1
3 98
4 98
01
0 26
0 26
g
0 1
V
CC
b
0 1
3 84
4 84
01
0 33
0 33
g
1 0
V
CC
b
0 1
37
47
01
04
04
g
1 0
V
V
V
V
V
V
mA
mA
mA
V
OL
Maximum Low Level
Voltage
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
40
03
40
04
80
05
Note 1
Absolute Maximum Ratings are those values beyond which damage to the device may occur
2
AC Electrical Characteristics
V
CC
e
5V
Symbol
f
MAX
Parameter
Maximum Operating
Frequency
T
A
e
25 C C
L
e
15 pF t
r
e
t
f
e
6 ns
Guaranteed
Units
Limit
30
30
30
20
10
b
3
Conditions Typ
50
18
18
MHz
ns
ns
ns
ns
ns
ns
t
PHL
t
PLH
Maximum Propagation
Delay from Clock to Q or Q
t
PHL
t
PLH
Maximum Propagation
Delay from Preset or Clear to Q or Q
t
REM
t
S
t
H
t
W
Minimum Removal Time
Preset or Clear to Clock
Minimum Setup Time
J or K Clock
Minimum Hold Time
Clock to J or K
Minimum Pulse Width
Clock Preset or Clear
20
0
16
8
AC Electrical Characteristics
V
CC
e
5 0V
g
10%
Symbol
Parameter
Conditions
C
L
e
50 pF t
r
e
t
f
e
6 ns (unless otherwise specified)
74HCT
T
A
eb
40 to 85 C
22
44
54HCT
T
A
eb
55 to 125 C
18
52
Units
T
A
e
25 C
Typ
Guaranteed Limits
27
MHz
ns
f
MAX
t
PHL
t
PLH
Maximum Operating
Frequency
Maximum Propagation
Delay from Clock to
Q or Q
Maximum Propagation
Delay from Preset
or Clear to Q or Q
Minimum Removal Time
Preset or Clear to Clock
Minimum Setup Time
J or K to Clock
Minimum Hold Time
Clock to J or K
Minimum Pulse Width
Clock Preset or Clear
Maximum Input Rise and
Fall Time
Maximum Output
Rise and Fall Time
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
(per flip-flop)
35
5
10
b
3
22
35
t
PHL
t
PLH
22
35
44
52
ns
t
REM
t
S
t
H
t
W
t
r
t
f
t
THL
t
TLH
C
PD
C
IN
20
20
0
16
500
15
25
25
0
20
500
19
30
30
0
24
500
22
ns
ns
ns
ns
ns
ns
pF
10
10
10
pF
Note 5
C
PD
determines the no load dynamic power consumption P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
and the no load dynamic current consumption I
S
e
C
PD
V
CC
f
a
I
CC
3
MM54HCT109 MM74HCT109 Dual J-K Flip-Flops with Preset and Clear
Physical Dimensions
inches (millimeters)
Order Number MM54HCT109J or MM74HCT109J
NS Package J16A
Order Number MM74HCT109N
NS Package N16E
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