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MM74HC138 3-to-8 Line Decoder
September 1983
Revised February 1999
MM74HC138
3-to-8 Line Decoder
General Description
The MM74HC138 decoder utilizes advanced silicon-gate
CMOS technology and is well suited to memory address
decoding or data routing applications. The circuit features
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
The MM74HC138 has 3 binary select inputs (A, B, and C).
If the device is enabled, these inputs determine which one
of the eight normally HIGH outputs will go LOW. Two active
LOW and one active HIGH enables (G1, G2A and G2B)
are provided to ease the cascading of decoders.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally and pin equiva-
lent to the 74LS138. All inputs are protected from damage
due to static discharge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 20 ns
s
Wide power supply range: 2V–6V
s
Low quiescent current: 80
µA
maximum (74HC Series)
s
Low input current: 1
µA
maximum
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC138M
MM74HC138SJ
MM74HC138MTC
MM74HC138N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
