MM54HC76 MM74HC76 Dual J-K Flip-Flops with Preset and Clear
January 1988
MM54HC76 MM74HC76 Dual J-K Flip-Flops
with Preset and Clear
General Description
These high speed (30 MHz minimum) J-K Flip-Flops utilize
advanced silicon-gate CMOS technology to achieve the low
power consumption and high noise immunity of standard
CMOS integrated circuits along with the ability to drive 10
LS-TTL loads
Each flip-flop has independent J K PRESET CLEAR and
CLOCK inputs and Q and Q outputs These devices are
edge sensitive to the clock input and change state on the
negative going transition of the clock pulse Clear and pre-
set are independent of the clock and accomplished by a low
logic level on the corresponding input
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical propagation delay 16 ns
Wide operating voltage range
Low input current 1
mA
maximum
Low quiescent current 40
mA
maximum (74HC Series)
High output drive 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Truth Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
J
X
X
X
L
H
L
H
X
L
X
X
X
L
L
H
H
X
Outputs
Q
Q
v
v
v
v
H
H
L
L
H
L
L
Q0
Q0
H
L
L
H
TOGGLE
Q0
Q0
This is an unstable condition and is not guaranteed
TL F 5074 – 1
Top View
Order Number MM54HC76 or MM74HC76
TL F 5074 – 3
TL F 5074 – 2
(1 of 2)
C
1995 National Semiconductor Corporation
TL F 5074
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
Operating Conditions
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
V
OUT
)
Operating Temp Range (T
A
)
MM74HC
MM54HC
Input Rise or Fall Times
(t
r
t
f
)
V
CC
e
2 0V
V
CC
e
4 5V
V
CC
e
6 0V
Min
2
0
Max
6
V
CC
Units
V
V
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
I
OK
)
b
0 5 to
a
7 0V
b
1 5 to V
CC
a
1 5V
b
0 5 to V
CC
a
0 5V
g
20 mA
b
40
b
55
a
85
a
125
C
C
ns
ns
ns
g
25 mA
DC Output Current per pin (I
OUT
)
g
50 mA
DC V
CC
or GND Current per pin (I
CC
)
b
65 C to
a
150 C
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
600 mW
S O Package only
500 mW
Lead Temp (T
L
) (Soldering 10 seconds)
260 C
1000
500
400
DC Electrical Characteristics
(Note 4)
Symbol
Parameter
Conditions
V
CC
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
20
mA
2 0V
4 5V
6 0V
4 5V
6 0V
2 0V
4 5V
6 0V
4 5V
6 0V
6 0V
6 0V
20
45
60
42
57
0
0
0
02
02
T
A
e
25 C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
15
3 15
42
05
1 35
18
19
44
59
3 98
5 48
01
01
01
0 26
0 26
g
0 1
74HC
T
A
eb
40 to 85 C
54HC
T
A
eb
55 to 125 C
Units
Guaranteed Limits
15
3 15
42
05
1 35
18
19
44
59
3 84
5 34
01
01
01
0 33
0 33
g
1 0
15
3 15
42
05
1 35
18
19
44
59
37
52
01
01
01
04
04
g
1 0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
V
IL
V
OH
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
4 0 mA
l
I
OUT
l
s
5 2 mA
V
OL
Maximum Low Level
Output Voltage
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
20
mA
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
4 0 mA
l
I
OUT
l
s
5 2 mA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
e
V
CC
or GND
V
IN
e
V
CC
or GND
I
OUT
e
0
mA
4
40
80
Note 1
Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2
Unless otherwise specified all voltages are referenced to ground
Note 3
Power Dissipation temperature derating
plastic ‘‘N’’ package
b
12 mW C from 65 C to 85 C ceramic ‘‘J’’ package
b
12 mW C from 100 C to 125 C
Note 4
For a power supply of 5V
g
10% the worst case output voltages (V
OH
and V
OL
) occur for HC at 4 5V Thus the 4 5V values should be used when designing
with this supply Worst case V
IH
and V
IL
occur at V
CC
e
5 5V and 4 5V respectively (The V
IH
value at 5 5V is 3 85V ) The worst case leakage current (I
IN
I
CC
and
I
OZ
) occur for CMOS at the higher voltage and so the 6 0V values should be used
V
IL
limits are currently tested at 20% of V
CC
The above V
IL
specification (30% of V
CC
) will be implemented no later than Q1 CY’89
2
AC Electrical Characteristics
V
CC
e
5V
Symbol
f
MAX
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
REM
t
s
t
H
t
W
Parameter
Maximum Operating Frequency
T
A
e
25 C C
L
e
15 pF t
r
e
t
f
e
6 ns
Conditions
Typ
50
16
21
23
10
14
b
3
Guaranteed Limit
30
21
26
28
20
20
0
16
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Maximum Propagation Delay Clock to Q or Q
Maximum Propagation Delay Clear to Q or Q
Maximum Propagation Delay Preset to Q or Q
Minimum Removal Time
Minimum Setup Time J or K to Clock
Minimum Hold Time J or K to Clock
Minimum Pulse Width Preset Clear or Clock
10
AC Electrical Characteristics
C
L
e
50 pF
Symbol
f
MAX
Parameter
Maximum Operating
Frequency
Maximum Propagation
Delay Clock to Q or Q
Maximum Propagation
Delay Clear to Q or Q
Maximum Propagation
Delay Preset to Q or Q
Minimum Removal Time
Preset or Clear
to Clock
Minimum Setup Time
J or K to Clock
Minimum Hold Time
J or K from Clock
Minimum Pulse Width
Preset Clear or Clock
Maximum Output Rise
and Fall Time
Maximum Input Rise and
Fall Time
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
(per flip-flop)
Conditions
V
CC
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25 C
Typ
9
45
53
100
20
17
126
25
21
137
27
23
55
11
9
77
15
13
b
3
b
3
b
3
74HC
T
A
eb
40 to 85 C
4
21
24
160
31
27
191
39
33
210
41
35
125
25
21
125
25
21
0
0
0
100
20
18
95
19
16
1000
500
400
54HC
T
A
eb
55 to 125 C
3
18
20
183
37
32
250
47
40
240
50
40
150
30
25
150
30
25
0
0
0
120
24
21
110
22
19
1000
500
400
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Guaranteed Limits
5
27
31
126
25
21
155
31
26
165
33
28
100
20
17
100
20
17
0
0
0
80
16
14
75
15
13
1000
500
400
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
REM
t
s
t
H
t
W
55
11
9
30
8
7
t
TLH
t
THL
t
r
t
f
C
PD
C
IN
80
5
10
10
10
pF
Note 5
C
PD
determines the no load dynamic power consumption P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
and the no load dynamic current consumption I
S
e
C
PD
V
CC
f
a
I
CC
3
Typical Applications
N Bit Presettable Ripple Counter with Enable and Reset
TL F 5074 – 4
N Bit Parallel Load Serial Load Shift Register with Clear
TL F 5074 – 5
4
Physical Dimensions
inches
(millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC76J or MM74HC76J
NS Package Number J16A
5
