These gates are monolithic complementary MOS (CMOS)
integrated circuits constructed with N- and P-channel en-
hancement mode transistors The MM70C95 MM80C95
and the MM70C97 MM80C97 convert CMOS or TTL out-
puts to TRI-STATE outputs with no logic inversion the
MM70C96 MM80C96 and the MM70C98 MM80C98 pro-
vide the logical opposite of the input signal The MM70C95
MM80C95 and the MM70C96 MM80C96 have common
TRI-STATE controls for all six devices The MM70C97
MM80C97 and the MM70C98 MM80C98 have two TRI-
STATE controls one for two devices and one for the other
four devices Inputs are protected from damage due to stat-
ic discharge by diode clamps to V
CC
and GND
Features
Y
Y
Y
Y
Wide supply voltage range
Guaranteed noise margin
High noise immunity
TTL compatible
3 0V to 15V
1 0V
0 45 V
CC
(typ )
Drive 1 TTL Load
Applications
Y
Bus drivers
Typical propagation delay
into 150 pF load is 40 ns
Connection Diagrams
(Dual-In-Line Packages)
MM70C95 MM80C95
MM70C96 MM80C96
TL F 5907 – 1
TL F 5907 – 2
Top View
Order Number MM70C95 or MM80C95
MM70C97 MM80C97
Top View
Order Number MM70C96 or MM80C96
MM70C98 MM80C98
TL F 5907 – 3
TL F 5907 – 4
Top View
Order Number MM70C97 or MM80C97
Top View
Order Number MM70C98 or MM80C98
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 5907
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
Operating Temperature Range
MM70CXX
MM80CXX
b
0 3V to V
CC
a
0 3V
b
55 C to
a
125 C
b
40 C to
a
85 C
Storage Temperature Range
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Power Supply Voltage (V
CC
)
Lead Temperature
(Soldering 10 seconds)
b
65 C to
a
150 C
700 mW
500 mW
18V
260 C
DC Electrical Characteristics
Min
Symbol
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
OZ
I
CC
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Output Current in High
Impedance State
Supply Current
Parameter
Max limits apply across temperature range unless otherwise noted
Conditions
Min
Typ
Max
Units
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
15V
35
80
15
20
45
90
05
10
0 005
b
1 0
b
0 005
V
V
V
V
V
V
V
V
mA
mA
10
15
mA
mA
mA
10
V
CC
e
15V V
O
e
15V
V
CC
e
15V V
O
e
0V
V
CC
e
15V
0 005
b
1 0
b
0 005
0 01
TTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
70C
80C
70C
80C
70C
80C
70C
80C
V
CC
e
4 5V
V
CC
e
4 75V
V
CC
e
4 5V
V
CC
e
4 75V
V
CC
e
4 5V I
O
e b
1 6 mA
V
CC
e
4 75V I
O
e b
1 6 mA
V
CC
e
4 5V I
O
e
1 6 mA
V
CC
e
4 75V I
O
e
1 6 mA
24
24
04
04
V
CC
b
1 5
V
CC
b
1 5
08
08
V
V
V
V
V
V
V
V
OUTPUT DRIVE (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
CC
e
5V V
IN(1)
e
5V
T
A
e
25 C V
OUT
e
0V
V
CC
e
10V V
IN(1)
e
10V
T
A
e
25 C V
OUT
e
0V
V
CC
e
5V V
IN(0)
e
0V
T
A
e
25 C V
OUT
e
V
CC
V
CC
e
10V V
IN(0)
e
0V
T
A
e
25 C V
OUT
e
V
CC
b
4 35
b
20
mA
mA
mA
mA
4 35
20
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the device should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
2
AC Electrical Characteristics
Symbol
t
pd0
t
pd1
Parameter
T
A
e
25 C C
L
e
50 pF unless otherwise noted
Conditions
Min
Typ
Max
Units
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95 MM80C95 MM70C97 MM80C97
MM70C96 MM80C96 MM70C98 MM80C98
V
CC
V
CC
V
CC
V
CC
e
e
e
e
5V
10V
5V
10V
60
25
70
35
100
40
150
75
ns
ns
ns
ns
t
pd0
t
pd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95 MM80C95 MM70C97 MM80C97
MM70C96 MM80C96 MM70C98 MM80C98
V
CC
V
CC
V
CC
V
CC
e
e
e
e
5V C
L
e
150 pF
10V C
L
e
150 pF
5V C
L
e
150 pF
10V C
L
e
150 pF
85
40
95
45
160
80
210
110
ns
ns
ns
ns
t
1H
t
0H
Delay from Disable Input to High Impedance
State (from Logical ‘‘1’’ or Logical ‘‘0’’)
MM70C95 MM80C95
MM70C96 MM80C96
MM70C97 MM80C97
MM70C98 MM80C98
R
L
e
10k C
L
e
5 pF
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
e
e
e
e
e
e
e
e
5V
10V
5V
10V
5V
10V
5V
10V
80
50
100
70
70
50
90
70
135
90
180
125
125
90
170
125
ns
ns
ns
ns
ns
ns
ns
ns
t
H1
t
H0
Delay from Disable Input to Logical ‘‘1’’ Level
(from High Impedance State)
MM70C95 MM80C95
MM70C96 MM80C96
MM70C97 MM80C97
MM70C98 MM80C98
R
L
e
10k C
L
e
50 pF
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
e
e
e
e
e
e
e
e
5V
10V
5V
10V
5V
10V
5V
10V
120
50
130
60
95
40
120
50
50
11
60
200
90
225
110
175
80
200
90
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance TRI-STATE
Power Dissipation Capacitance
Any Input (Note 2)
Any Output (Note 2)
(Note 3)
AC Parameters are guaranteed by DC correlated testing
