MMCP-67204HV-15,MMCP-67204HV-15 pdf中文资料,MMCP-67204HV-15引脚图,MMCP-67204HV-15电路-Datasheet-电子工程世界

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Features

•

First-in First-out Dual Port Memory

4096-bit x 9 Organization

Fast Flag and Access Times: 15, 30 ns

Wide Temperature Range: -55°C to +125°C

Fully Expandable by Word Width or Depth

Asynchronous Read/Write Operations

Empty, Full and Half Flags in Single Device Mode

Retransmit Capability

Bi-directional Applications

Battery Backup Operation: 2V Data Retention

TTL Compatible

Single 5V ± 10% Power Supply

No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm

Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019

QML Q and V with SMD 5962-89568

ESCC B with specification 9301/049

Rad. Tolerant

High Speed

4 Kb x 9

Parallel FIFO

M67204H

Description

The M67204H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information is required for the Atmel FIFOs.

address pointers are automatically incremented with the write pin and read pin. The 9

bits wide data are used in data communications applications where a parity bit for

error checking is necessary. The retransmit pin reset the read pointer to zero without

affecting the write pointer. This is very useful for retransmitting data when an error is

detected in the system.

Using an array of eight transistors (8T) memory cell, the M67204H combines an

extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2 µW.

The M67204H is processed according to the methods of the latest revision of the MIL

PRF 38535 (Q and V) or ESA SCC 9000.

4141I–AERO–06/04

Block Diagram

Pin Configuration

DIL ceramic 28-pin 300 mils

FP 28-pin 400 mils

M67204H

4141I–AERO–06/04

M67204H

Pin Description

Names

XO/HF

FL/RT

VCC

GND

I0-8

Q0-8

Description

Full Flag

Expansion Out/Half-Full Flag

Expansion IN

First Load/Retransmit

Power Supply

Ground

Inputs

Outputs

Write Enable

Read Enable

Reset

Empty Flag

Data In (I

- I

)

Reset (RS)

Data inputs for 9-bit data

Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both

internal read and write pointers to the first location. A reset is required after power-up

before a write operation can be enabled. Both the Read Enable (R) and Write Enable

(W) inputs must be in the high state during the period shown in Figure 1 (i.e. t

RSS

before

the rising edge of RS) and should not change until t

RSR

after the rising edge of RS. The

Half-Full Flag (HF) will be reset to high After Reset (RS).

Figure 1.

Reset

Notes:

1. EF, FF and HF may change status during reset, but flags will be valid at t

RSC

2. W and R = VIH around the rising edge of RS.

4141I–AERO–06/04

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not with

standing any current write operations. After Read Enable (R) goes high, the Data Out-

puts (Q0 - Q8) will return to a high impedance state until the next Read operation. When

all the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing

the “final” read cycle, but inhibiting further read operations whilst the data outputs

remain in a high impedance state. Once a valid write operation has been completed, the

Empty Flag (EF) will go high after tWEF and a valid read may then be initiated. When

the FIFO stack is empty, the internal read pointer is blocked from R, so that external

changes to R will have no effect on the empty FIFO stack.

This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M67204H can be made to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes equals to or less than the depth of the FIFO has occured since the last

RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode and

will affect the Half-Full Flag (HF), in accordance with the relative locations of the read

and write pointers.

First Load/Retransmit

(FL/RT)

Expansion In (XI)

This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 4096 writes.

The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

Full Flag (FF)

Empty Flag (EF)

M67204H

4141I–AERO–06/04

M67204H

Expansion Out/Half-full

Flag (XO/HF)

This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-

nected to ground, this output acts as an indication of a half-full memory.

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Flag (HF) will be set to low and will remain set until the difference between the

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device reaches the last memory

location.

Data Output (Q

- Q

)

DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

4141I–AERO–06/04

参数对比

与MMCP-67204HV-15相近的元器件有：SMDP-67204HV-30SB、SMCP-67204HV-30SB、MMCP-67204HV-30、MMDP-67204HV-30、SMDP-67204HV-15SB、MMDP-67204HV-15、SMCP-67204HV-15SB。描述及对比如下：

型号	MMCP-67204HV-15	SMDP-67204HV-30SB	SMCP-67204HV-30SB	MMCP-67204HV-30	MMDP-67204HV-30	SMDP-67204HV-15SB	MMDP-67204HV-15	SMCP-67204HV-15SB
描述	FIFO, 4KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	FIFO, 4KX9, 30ns, Asynchronous, CMOS, 0.400 INCH, FP-28	FIFO, 4KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	FIFO, 4KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	FIFO, 4KX9, 30ns, Asynchronous, CMOS, 0.400 INCH, FP-28	FIFO, 4KX9, 15ns, Asynchronous, CMOS, 0.400 INCH, FP-28	FIFO, 4KX9, 15ns, Asynchronous, CMOS, 0.400 INCH, FP-28	FIFO, 4KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28
是否无铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	DIP	DFP	DIP	DIP	DFP	DFP	DFP	DIP
包装说明	DIP, DIP28,.3	DFP, FL28,.4	DIP, DIP28,.3	DIP, DIP28,.3	DFP, FL28,.4	DFP, FL28,.4	DFP, FL28,.4	DIP, DIP28,.3
针数	28	28	28	28	28	28	28	28
Reach Compliance Code	compliant	compliant	compliant	compliant	compli	compli	compli	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	15 ns	30 ns	30 ns	30 ns	30 ns	15 ns	15 ns	15 ns
周期时间	25 ns	40 ns	40 ns	40 ns	40 ns	25 ns	25 ns	25 ns
JESD-30 代码	R-CDIP-T28	R-XDFP-F28	R-CDIP-T28	R-CDIP-T28	R-XDFP-F28	R-XDFP-F28	R-XDFP-F28	R-CDIP-T28
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0
内存密度	36864 bit	36864 bit	36864 bit	36864 bit	36864 bi	36864 bi	36864 bi	36864 bi
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
内存宽度	9	9	9	9	9	9	9	9
功能数量	1	1	1	1	1	1	1	1
端子数量	28	28	28	28	28	28	28	28
字数	4096 words	4096 words	4096 words	4096 words	4096 words	4096 words	4096 words	4096 words
字数代码	4000	4000	4000	4000	4000	4000	4000	4000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
组织	4KX9	4KX9	4KX9	4KX9	4KX9	4KX9	4KX9	4KX9
可输出	NO	NO	NO	NO	NO	NO	NO	NO
封装主体材料	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED
封装代码	DIP	DFP	DIP	DIP	DFP	DFP	DFP	DIP
封装等效代码	DIP28,.3	FL28,.4	DIP28,.3	DIP28,.3	FL28,.4	FL28,.4	FL28,.4	DIP28,.3
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	FLATPACK	IN-LINE	IN-LINE	FLATPACK	FLATPACK	FLATPACK	IN-LINE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.94 mm	3.3 mm	3.94 mm	3.94 mm	3.3 mm	3.3 mm	3.3 mm	3.94 mm
最大待机电流	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A	0.005 A
最大压摆率	0.12 mA	0.11 mA	0.11 mA	0.11 mA	0.11 mA	0.12 mA	0.12 mA	0.12 mA
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	YES	NO	NO	YES	YES	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	THROUGH-HOLE	FLAT	THROUGH-HOLE	THROUGH-HOLE	FLAT	FLAT	FLAT	THROUGH-HOLE
端子节距	2.54 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
总剂量	30k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V
宽度	7.62 mm	10.16 mm	7.62 mm	7.62 mm	10.16 mm	10.16 mm	10.16 mm	7.62 mm
厂商名称	Atmel (Microchip)	-	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)