MO9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethern
et
Features
Applications
0.3 ps RMS phase jitter (random) for 10GbE applications
Frequency stability as low as
±10
ppm
100% drop-in replacement for quartz and SAW oscillators
Configurable positive frequency shift, +25, +50, or +75 ppm
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mmxmm
Best in class 1-year and 10-year aging
Best resilience, up to 40x better than quartz
For other frequencies, refer to SiT9121 or 9122 datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Telecom, networking, instrumentation, storage, servers
Electrical Characteristics
Parameter and Conditions
Symbol
Min.
+2.97
Supply Voltage
Vdd
+2.25
+2.25
Output Frequency Range
f
Typ.
+3.3
+2.5
–
Max.
+3.63
+2.75
+3.63
Unit
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
kΩ
MΩ
ms
ms
%
+25°C
+25°C
Industrial
Extended Commercial
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time
ST
pin crosses
50% threshold.
Contact KDS for tighter duty cycle
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
Termination schemes in Figures 1 and 2 - XX ordering code
156.253906 MHz, +25 PPM from 156.250000
156.257812 MHz, +50 PPM from 156.250000
156.261718 MHz, +75 PPM from 156.250000
Condition
LVPECL and LVDS, Common Electrical Characteristics
156.25000, 156.253906,
156.257812, 156.261718,
161.132800
-10
–
–
–
–
–
–
–
–
–
–
100
–
6.0
6.0
–
+10
+20
+25
+50
+2.0
+5.0
+85
+70
–
30%
250
–
10
10
55
-20
-25
-50
-2.0
-5.0
-40
-20
70%
–
–
2.0
–
–
45
–
–
–
–
–
Vdd-1.1
Vdd-1.9
+1.2
–
–
–
–
–
+250
Frequency Stability
F_stab
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
F_aging1
F_aging10
T_use
VIH
VIL
Z_in
Start-up Time
Resume Time
Duty Cycle
T_start
T_resume
DC
LVPECL, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Phase Jitter (random)
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_phj
+61
–
–
–
–
–
–
+1.6
300
–
0.25
+69
+35
+1.0
+100
+30
Vdd-0.7
Vdd-1.5
+2.0
500
120
0.3
mA
mA
μA
μA
mA
V
V
V
ps
ns
ps
Excluding Load Termination Current, Vdd = +3.3V or +2.5V
OE = Low
OE = Low
ST
= Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 156.25 MHz - For other frequencies, T_oe = 100ns + 3 period
IEEE802.3-2005 10GbE jitter measurement specifications
LVDS, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Idd
I_OE
VOD
+47
–
+350
+55
+35
+450
mA
mA
mV
Excluding Load Termination Current, Vdd = +3.3V or +2.5V
OE = Low
See Figure 2
Daishinku Corp.
Rev. 1.06
1389 Shinzaike, Hiraoka-cho, Kakogawa, Hyogo 675-0194 Japan
+81-79-426-3211
www.kds.info
Revised October 6, 2014
MO9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethern
et
Electrical Characteristics
(continued)
Parameter and Conditions
Symbol
Min.
–
–
–
+1.125
–
–
–
–
Typ.
–
–
–
+1.2
–
495
–
0.25
Max.
Unit
μA
μA
mV
V
mV
ps
ns
ps
Condition
LVDS, DC and AC Characteristics (continued)
Output Disable Leakage Current
Standby Current
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
OE Enable/Disable Time
RMS Phase Jitter (random)
I_leak
I_std
VOD
VOS
VOS
Tr, Tf
T_oe
T_phj
+1.0
+100
+50
+1.375
+50
600
115
0.3
OE = Low
ST
= Low, for all Vdds
See Figure 2
See Figure 2
See Figure 2
20% to 80%, see Figure 2
f = 156.25 MHz - For other frequencies, T_oe = 100ns + 3 period
IEEE802.3-2005 10GbE jitter measurement specifications
Pin Description
Pin
Map
OE
1
ST
Input
Input
Functionality
H or Open: specified frequency output L:
output is high impedance
H or Open: specified frequency output
L: Device goes to sleep mode. Supply current reduces to I_std.
No Connect; Leave it floating or connect to GND for better heat
dissipation
VDD Power Supply Ground
Oscillator output
Complementary oscillator output
Power supply voltage
Top View
OE/ST
NC
GND
1
6
VDD
OUT-
OUT+
2
3
4
5
6
NC
GND
OUT+
OUT-
VDD
NA
Power
Output
Output
Power
2
5
3
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge (HBM)
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
+150
+4.0
+2000
+260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050, 6-pin
5032, 6-pin
3225, 6-pin
JA, 4 Layer Board
(°C/W)
142
97
109
JC, Bottom
(°C/W)
27
20
20
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.06
Page 2 of 8
www.kds.info
MO9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethern
et
Waveform Diagrams
OUT-
80%
80%
20%
OUT+
20%
VOH
VOL
Tr
Tf
GND
Figure 1(a). LVPECL Voltage Levels per Differential Pin (OUT+/OUT-)
V_ S w ing
0 V
t
Figure 1(b). LVPECL Voltage Levels Across Differential Pair
OUT-
80%
VOD
80%
20%
OUT+
20%
VOS
Tr
GND
Tf
Figure 2. LVDS Voltage Levels per Differential Pin (OUT+/OUT-)
Rev. 1.06
Page 3 of 8
www.kds.info
MO9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethern
et
Termination Diagrams
LVPECL:
VDD
Z0 = 50
Ω
OUT+
LVPECL Driver
OUT-
D+
Receiver Device
Z0 = 50
Ω
50
Ω
50
Ω
D-
VTT = VDD – 2.0 V
Figure 3. LVPECL Typical Termination
VDD
OUT+
LVPECL Driver
VDD= 3.3V => R1 = 100 to 150 Ω
VDD= 2.5V => R1 = 75 Ω
100 nF
D+
Receiver Device
100 nF
Z0 = 50 Ω
OUT-
R1
R1
Z0 = 50 Ω
50 Ω
50 Ω
D-
VTT
Figure 4. LVPECL AC Coupled Termination
VDD = 3.3V => R1 = R3 = 133 Ω and
R2 = R4 = 82 Ω
VDD
VDD = 2.5V => R1 = R3 = 250 Ω and
R2 = R4 = 62.5 Ω
VDD
OUT+
LVPECL Driver
OUT-
Z0 = 50 Ω
R2
R4
Z0 = 50 Ω
R1
R3
D+
Receiver Device
D-
Figure 5. LVPECL with Thevenin Typical Termination
Rev. 1.06
Page 4 of 8
www.kds.info
MO9156
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethern
et
LVDS:
VDD
OUT+
LVDS Driver
OUT-
Z0 = 50
Ω
100
Ω
Z0 = 50
Ω
D+
Receiver Device
D-
Figure 6. LVDS Single Termination (Load Terminated)
Rev. 1.06
Page 5 of 8
www.kds.info
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