MOD-ENC624J600 development board
Users Manual
All boards produced by Olimex are ROHS compliant
Rev. A, June 2011
Copyright(c) 2011, OLIMEX Ltd, All rights reserved
Page 1
INTRODUCTION
MOD-ENC624J600
is development board with UEXT connector and 100 Mbit
ENC624J600 ethernet controller from Microchip Technology Inc.
BOARD FEATURES
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MOD-ENC624J600 is the easiest way to add 100 Mbit ethernet connectivity to
any of our boards with UEXT connector
ENC624J600 Ethernet controller with UEXT connector for easy connection to
our other development boards with UEXT connector
LAN connector with build in transformer
two status LEDs on LAN connector
SPI/PARALLEL port interface to add Ethernet interface to your microcontroller
project
UEXT 10 pin interface on 0.1" row pins header
PCB: FR-4, 1.5 mm (0,062"), soldermask, white silkscreen component print
Dimensions: 46.99x36.83 mm (1.85 x 1.45")
ELECTROSTATIC WARNING
The MOD-ENC624J600 board is shipped in protective anti-static packaging. The
board must not be subject to high electrostatic potentials. General practice for
working with static sensitive devices should be applied when working with this
board.
BOARD USE REQUIREMENTS
Hardware:
Our development board PIC 32-WEB use ENC624J600
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ETHERNET CONTROLLER FEATURES
MOD-ENC28J60
board use ENC624J600 stand-alone ethernet controller with these
features:
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IEEE 802.3™ Compliant Fast Ethernet Controller
Integrated MAC and 10/100Base-T PHY
Hardware Security Acceleration Engines
24-Kbyte Transmit/Receive Packet Buffer SRAM
Supports one 10/100Base-T Port with Automatic Polarity Detection and
Correction
Supports Auto-Negotiation
Support for Pause Control Frames, including Automatic Transmit and Receive
Flow Control
Supports Half and Full-Duplex Operation
Programmable Automatic Retransmit on Collision
Programmable Padding and CRC Generation
Programmable Automatic Rejection of Erroneous and Runt Packets
Factory Preprogrammed Unique MAC Address
MAC:
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Support for Unicast, Multicast and Broadcast packets
Supports promiscuous reception
Programmable pattern matching
Programmable filtering on multiple packet formats, including Magic
Packet™, Unicast, Multicast, Broadcast, specific packet match,
destination address hash match or any packet
Wave shaping output filter
Internal Loopback mode
Energy Detect Power-Down mode
High-performance, modular exponentiation engine with up to 1024-bit
operands
Supports RSA
®
and Diffie-Hellman key exchange algorithms
High-performance AES encrypt/decrypt engine with 128-bit, 192-bit or
256-bit key
Hardware AES ECB, CBC, CFB and OFB mode capability
Software AES CTR mode capability
Fast MD5 hash computations
Fast SHA-1 hash computations
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PHY:
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Security Engines:
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Buffer:
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Configurable transmit/receive buffer size
Hardware-managed circular receive FIFO
8-bit or 16-bit random and sequential access
High-performance internal DMA for fast memory copying
High-performance hardware IP checksum calculations
Accessible in low-power modes
Space can be reserved for general purpose application usage in addition
to transmit and receive packets
Outputs for two LED indicators with support for single and dual LED
configurations
Transmit and receive interrupts
25MHz clock
5V tolerant inputs
Clock out pin with programmable frequencies from 50 kHz to 33.3
MHz
Operating voltage range of 3.0V to 3.6V
Temperature range: -40°C to +85°C industrial
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Operational:
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BLOCK DIAGRAM
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单片机
