MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MPC27T416/D
Advance Information
MPC27T416
16K x 16 Bit Cache Tag RAM
for PowerPC™ Processors
The MPC27T416 is a 262,144 bit cache–tag static RAM designed to support
PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K
words of 16 bits each and is fabricated using Motorola‘s high performance, silicon
gate BiCMOS technology. There are fourteen common I/O tag bits and two separate
I/O status bits. A 14–bit comparator is on–chip to allow fast comparison of the 14
stored tag bits with the current tag input data. An active high MATCH output is
generated when the valid bit is true and these two groups of data are the same for
a given address.
This high–speed MATCH signal, with tAVMV times as fast as 9 ns, provides the
fastest possible enabling of secondary cache accesses.
The two separate I/O status bits (VALID, DIRTY) can be configured for either
dedicated or generic functionality, depending on the SFUNC input pin. With SFUNC
low, the status bits are defined and used internally by the device, allowing easier
determination of the validity and use of the given tag data. SFUNC high releases the
defined internal status bit usage and control, allowing users to configure the status
bit information to fit their system needs. A synchronous RESET pin, when held low
at a rising clock edge, will reset all status bits in the array for easy invalidation of all
tag addresses.
The MPC27T416 also provides the option for transfer acknowledge (TA)
generation within the cache tag itself, based upon MATCH, VALID bit, and other
external inputs provided by the user. This can significantly simplify cache controller
logic and minimize cache decision time. Match and read operations are both
asynchronous in order to provide the fastest access times possible, while write
operations are synchronous for ease of system timing.
The MPC27T416 uses a 5 V power supply on VCC and VSS, with separate VCCQ
pins provided for the outputs to offer compliance with both 5 V TTL and 3.3 V LVTTL
logic levels. The PWRDN pin offers a low–power standby mode, which provides
significant system power savings.
The MPC27T416 is offered in a space saving 80–pin thin quad flat pack (TQFP)
package.
•
16K x 16 Configuration:
– 14 Tag Bits
– Two Status Bits (Valid and Dirty)
•
Valid Bit used to Qualify Match Output
•
High–Speed Address–to–Match Comparison Times – 9/10/12 ns
•
TA Circuitry Included Inside the Cache–Tag for the Highest Speed Operation
•
Asynchronous Read/Match Operation and Synchronous Write and Reset
Operation
•
Separate Write Enable Pins for Tag Bits and Status Bits
•
Separate Output Enable Pins for Tag Bits, Status Bits, and TA
•
Synchronous RESET Pin for Invalidation of all Tag Entries
•
Dual Chip Selects for Easy Depth Expansion with No Performance
Degradation
•
I/O Pins Both 5 V TTL and 3.3 V LVTTL Compatible with VCCQ Pins
•
PWRDN Pin to Place Device in Low–Power Mode
•
Compatible with PowerPC Platform (CHRP)
•
Packaged in a 80–Pin Thin Quad Flat Pack (TQFP)
TQ PACKAGE
TQFP
CASE 917A–02
PowerPC is a trademark of IBM Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
4/26/96
©
Motorola, Inc. 1996
MOTOROLA FAST SRAM
MPC27T416
1
FUNCTIONAL BLOCK DIAGRAM
A0 – A13
REG
0
1
16K x 14
MEMORY
TAG BITS
16K x 2
MEMORY
STATUS BITS
E1
E2
REG
DATA IN
REGISTER
SA
SA
DATA IN
REGISTER
VALIDD
DIRTYD
TDQ0–TDQ13
GT
VALIDQ
DIRTYQ
WRITE (pos) PULSE
GENERATOR
WT
WS
K
REG
RESET (neg) PULSE
GENERATOR
COMPARE
GS
RESET
PWRDN
SFUNC
MATCH
TT1
TAH
TAD
TA
REG
TAG
MPC27T416
2
MOTOROLA FAST SRAM
PIN ASSIGNMENTS
VALIDD
VCC
VSS
PWRDN
E2
E1
WT
WS
VCC
VSS
RESET
K
GS
GT
TAG
TDQ13
VSS
TDQ12
VCCQ
TDQ11
VSS
VSS
VSS
VSS
DIRTYD
NC
A0
A1
A2
VCC
VSS
A3
A4
A5
A6
A7
VSS
VSS
VSS
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A8
SFUNC
TT1
VSS
VCC
VCC
TAH
TAD
A9
A10
A11
A12
A13
DIRTYQ
TDQ0
VSS
TDQ1
VCCQ
TDQ2
TDQ3
VSS
VSS
VSS
TDQ10
TDQ9
TDQ8
VALIDQ
VCCQ
VSS
TA
MATCH
VSS
VCCQ
TDQ7
TDQ6
TDQ5
TDQ4
VSS
VSS
VSS
MOTOROLA FAST SRAM
MPC27T416
3
PIN DESCRIPTIONS
Pin Locations
7, 8, 9, 12, 13, 14, 15, 16, 21,
29, 30, 31, 32, 33,
75, 76
Symbol
A0 – A13
Type
Input
Description
Address Inputs: These inputs are registered and must meet setup and
hold times for write cycles only. For all other cycles, addresses are
asynchronous.
Chip Selects: These inputs are registered and must meet setup and
hold times for write cycles only. For all other cycles, E1 and E2 are
asynchronous.
Clock: This signal registers the address, data in, and all control signals
except G, TAH, TT1, SFUNC, and PWRDN.
Write Enable–Tag Bits: This input is registered and must meet setup and hold
times for all cycles this chip is selected.
Write Enable–Status Bits: This input is registered and must meet setup and
hold times for all cycles this chip is selected.
Output Enable–Tag Bits: Asynchronous, active low.
Output Enable–Status Bits: Asynchronous, active low.
Status Bit Reset: Reset cycle is initiated synchronously on a rising clock edge
and will terminate within the Status Bit Reset Time. When RESET is returned
high, the part will return to normal operation within the time specified in the
RESET AC Cycle Timing table.
Powerdown Mode Control Pin: This signal is asynchronous and places the
RAM in standby mode.
Status Bit Function Control Pin
Read/Write Input from Processor
Valid Bit Input
Dirty Bit Input
No Connection to the Chip
Transfer Acknowledge: Typically used as “ready” signal to processor for cache
reads. Can also be used as an active low MATCH pin.
TA Force High: Active high signal places TA into high–Z mode.
TA Output Enable: Asynchronous, active low.
Additional TA Input
Tag Data Input/Outputs: Used as input port for compare cycles. Used as
output port for tag read cycles.
Valid Bit Output
Dirty Bit Output
Match: This pin is asserted high when the selected tag’s valid bit is true, and
the stored tag in the RAM array matches the tag data presented on the TDQ
pins.
Power Supply: 5.0 V
±
5%
Output Buffer Power Supply: 5 V
±
5% or 3.3 V
±
0.3 V.
Ground
E1, E2
Input
69
74
73
67
68
70
K
WT
WS
GT
GS
RESET
Input
Input
Input
Input
Input
Input
77
22
23
80
5
6
51
27
66
28
35, 37, 39, 40, 44, 45, 46, 47,
55, 56, 57, 61, 63, 65,
54
34
50
PWRDN
SFUNC
TT1
VALIDD
DIRTYD
NC
TA
TAH
TAG
TAD
TDQ0–
TDQ13
VALIDQ
DIRTYQ
MATCH
Input
Input
Input
Input
Input
—
Output
Input
Input
Input
I/O
Output
Output
Output
10, 25, 26, 72, 79
38, 48, 53, 62
1, 2, 3, 4, 11, 17, 18, 19, 20,
24, 36, 41, 42, 43, 49, 52, 58,
59, 60, 64, 71, 78
VCC
VCCQ
VSS
Supply
Supply
Supply
MPC27T416
4
MOTOROLA FAST SRAM
HIP SELECT FUNCTION TRUTH TABLE
(See Notes 1 and 2)
Next Cycle
Deselect
Deselect
Select
E1
H
X
L
E2
X
L
H
RESET
X
X
X
PWRDN
H
H
H
K
X
X
X
WT
X
X
X
WS
X
X
X
TAG
X
X
X
TDQ
High–Z
High–Z
—
VALIDQ
High–Z
High–Z
—
DIRTYQ
High–Z
High–Z
—
MATCH
High–Z
High–Z
—
TA
High–Z
High–Z
—
POWER
Active
Active
Active
RESET FUNCTION TRUTH TABLE
(See Notes 1 and 2)
Next Cycle
Reset Status
Reset Status
Reset Status
Reset Status
Not Allowed
Not Allowed
E1
L
L
H
X
X
X
E2
H
H
X
L
X
X
RESET
L
L
L
L
L
L
PWRDN
H
H
H
H
H
H
K
WT
H
H
H
H
L
X
WS
H
H
H
H
X
L
TAG
L
H
X
X
X
X
TDQ
High–Z
High–Z
High–Z
High–Z
—
—
VALIDQ
L(3)
L(3)
High–Z
High–Z
—
—
DIRTYQ
L(3)
L(3)
High–Z
High–Z
—
—
MATCH
L
L
High–Z
High–Z
—
—
TA
H(4)
High–Z
High–Z
High–Z
—
—
POWER
Active
Active
Active
Active
—
—
°
°
°
°
°
°
POWER–DOWN FUNCTION TRUTH TABLE
(See Notes 1 and 2)
Next Cycle
Standby
NOTES: 1.
2.
3.
4.
E1
X
E2
X
RESET
X
PWRDN
L
K
X
WT
H
WS
H
TAG
X
TDQ
High–Z
VALIDQ
High–Z
DIRTYQ
High–Z
MATCH
High–Z
TA
High–Z
POWER
Power–
down
X = Don’t Care, H = VIH, L = VIL, “—” = Undefined.
GT, GS, TT1, TAH, and SFUNC are X for this table.
GS is low.
TA output is dependent on the previous registered value of TAD.
READ FUNCTION TRUTH TABLE
(See Notes 1 and 2)
Cycle Type
Read Tag I/O
Read Status Bits
Tag I/O Disable
Status Disable
GT
L
X
H
X
GS
X
L
X
H
WT
H
X
X
X
WS
X
X
X
X
K
X
X
X
X
TT1
X
X
X
X
TDQ
Dout
—
High–Z
—
VALIDD
—
—
—
—
DIRTYD
—
—
—
—
VALIDQ
—
Dout
—
High–Z
DIRTYQ
—
Dout
—
High–Z
MATCH
L
—
—
—
WRITE FUNCTION TRUTH TABLE
(See Notes 1 and 2)
Cycle Type
Write Tag I/O
Not Allowed
Write Status Bits
Write Status Bits
GT
H
L
X
X
GS
X
X
L
H
WT
L
L
X
X
WS
X
X
L
L
K
TT1
X
X
X
X
TDQ
Din
—
—
—
VALIDD
—
—
Din
Din
DIRTYD
—
—
Din
Din
VALIDQ
—
—
Dout(3)
High–Z
DIRTYQ
—
—
Dout(3)
High–Z
MATCH
L
—
L
L
°
°
°
°
NOTES: 1. X = Don’t Care, H = VIH, L = VIL, “—” = Undefined.
2. This table applies when E1 is low, and E2, RESET, and PWRDN are high. TAG, TAH, TAD, and SFUNC are X for this table.
3. Dout in this case is the same as Din; the input data is written through to the outputs during the write operation.
MATCH FUNCTION TRUTH TABLE
(See Notes 1 and 3)
Next Cycle
Deselect
Deselect
Select
Read Tag I/O
Write Tag I/O
Write Status Bits
Invalid Data–Dedicated Status Bits
Match–Dedicated Status Bits
E1
H
X
L
L
L
L
L
L
E2
X
L
H
H
H
H
H
H
SFUNC
X
X
X
X
X
X
L
L
GT
X
X
X
L
H
X
H
H
WT
X
X
X
H
L
X
H
H
WS
X
X
X
X
X
L
H
H
TDQ
High–Z
High–Z
—
Dout
Din
—
TDQin
TDQin
VALIDQ(4)
—
—
—
—
—
Din
L
H
DIRTYQ(4)
—
—
—
—
—
Din
—
—
MATCH
High–Z
High–Z
—
L
L
L
L
M(2)
Match–Generic Status Bits
L
H
H
H
H
H
TDQin
X
—
M(2)
NOTES: 1. X = don’t care, H = VIH, L = VIL, “—” = Undefined.
2. M = high if TDQin equals the memory contents at that address; M = low if TDQin does not equal the memory contents at that address.
3. PWRDN and RESET are high for this table. TT1, TAH, TAG, TAD, GS, and K are X.
4. This column represents the stored memory cell data for the given status bit at the selected address.
MOTOROLA FAST SRAM
MPC27T416
5
淘e淘
