NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5604BC
Rev. 14, 11/2017
MPC5604B/C
MPC5604B/C
Microcontroller Data Sheet
208 MAPBGA (17 x 17 x 1.7 mm)
144 LQFP (20 x 20 x 1.4 mm)
100 LQFP (14 x 14 x 1.4 mm)
64 LQFP (10 x 10 x 1.4 mm)
Features
• Single issue, 32-bit CPU core complex (e200z0)
– Compliant with the Power Architecture
®
embedded
category
– Includes an instruction set enhancement allowing
variable length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed 16-bit
and 32-bit instructions, it is possible to achieve
significant code size footprint reduction.
• Up to 512 KB on-chip code flash supported with the flash
controller and ECC
• 64 (4 × 16) KB on-chip data flash memory with ECC
• Up to 48 KB on-chip SRAM with ECC
• Memory protection unit (MPU) with 8 region descriptors
and 32-byte region granularity
• Interrupt controller (INTC) with 148 interrupt vectors,
including 16 external interrupt sources and 18 external
interrupt/wakeup sources
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash memory, or RAM from multiple bus
masters
• Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a range of
16-bit input capture, output compare, and pulse width
modulation functions (eMIOS-lite)
• 10-bit analog-to-digital converter (ADC)
• 3 serial peripheral interface (DSPI) modules
• Up to 4 serial communication interface (LINFlex)
modules
• Up to 6 enhanced full CAN (FlexCAN) modules with
configurable buffers
• 1 inter IC communication interface (I
2
C) module
• Up to 123 configurable general purpose pins supporting
input and output operations (package dependent)
• Real Time Counter (RTC) with clock source from128 kHz
or 16 MHz internal RC oscillator supporting autonomous
wakeup with 1 ms resolution with max timeout of 2
seconds
• Up to 6 periodic interrupt timers (PIT) with 32-bit counter
resolution
• 1 System Module Timer (STM)
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
• Device/board boundary Scan testing supported with per
Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
• On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 Pad configuration during reset phases . . . . . . . . . . . . .11
2.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .31
2.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .31
2.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.11.1 NVUSRO[PAD3V5V] field description . . . . . . . .32
2.11.2 NVUSRO[OSCILLATOR_MARGIN] field description
32
2.11.3 NVUSRO[WATCHDOG_EN] field description . .32
2.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .33
2.13 Recommended operating conditions . . . . . . . . . . . . . .34
2.14 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .36
2.14.1 Package thermal characteristics . . . . . . . . . . . .36
2.14.2 Power considerations. . . . . . . . . . . . . . . . . . . . .37
2.15 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .37
2.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.15.2 I/O input DC characteristics . . . . . . . . . . . . . . . .38
2.15.3 I/O output DC characteristics. . . . . . . . . . . . . . .39
2.15.4 Output pin transition times . . . . . . . . . . . . . . . . .42
2.15.5 I/O pad current specification . . . . . . . . . . . . . . .42
2.16 RESET electrical characteristics. . . . . . . . . . . . . . . . . .48
2.17 Power management electrical characteristics. . . . . . . .51
2.17.1 Voltage regulator electrical characteristics . . . .51
2.17.2 Low voltage detector electrical characteristics .56
2.18 Power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.19 Flash memory electrical characteristics . . . . . . . . . . . .59
2.20
2.19.1 Program/Erase characteristics . . . . . . . . . . . . . 59
2.19.2 Flash power supply DC characteristics . . . . . . 60
2.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 61
Electromagnetic compatibility (EMC) characteristics. . 61
2.20.1 Designing hardened software to avoid noise
problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.20.2 Electromagnetic interference (EMI) . . . . . . . . . 62
2.20.3 Absolute maximum ratings (electrical sensitivity)62
Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 68
Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
72
72
72
77
79
79
80
86
87
88
88
89
92
95
97
99
99
2.21
2.22
2.23
2.24
2.25
3
4
5
2.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . .
2.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.26.2 Input impedance and ADC accuracy . . . . . . . .
2.26.3 ADC electrical characteristics . . . . . . . . . . . . .
2.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.27.1 Current consumption . . . . . . . . . . . . . . . . . . . .
2.27.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . .
2.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . .
2.27.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . .
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . .
3.1.1 64 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPC5604B/C Microcontroller Data Sheet, Rev. 14
2
NXP Semiconductors
1
1.1
Introduction
Introduction
3
MPC5604B/C Microcontroller Data Sheet, Rev. 14
NXP Semiconductor s
Document overview
This document describes the features of the family and options available within the family members, and highlights important electrical and physical
characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet.
1.2
Description
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture
®
embedded category.
The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family
of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host
processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length
encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating
systems and configuration code to assist with users implementations.
Table 1. MPC5604B/C device comparison
1
Device
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC5604
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL BxMG
e200z0h
Static – up to 64 MHz
256 KB
384 KB
64 KB (4 × 16 KB)
24 KB
32 KB
28 KB
8-entry
12 ch
28 ch
36 ch
8 ch
28 ch
12 ch
28 ch
36 ch
8 ch
Yes
12 ch,
16-bit
2 ch
28 ch,
16-bit
5 ch
56 ch,
16-bit
10 ch
12 ch,
16-bit
2 ch
28 ch,
16-bit
5 ch
12 ch,
16-bit
2 ch
28 ch,
16-bit
5 ch
56 ch,
16-bit
10 ch
12 ch,
16-bit
2 ch
28 ch,
16-bit
5 ch
12 ch,
16-bit
2 ch
28 ch,
16-bit
5 ch
56 ch,
16-bit
10 ch
12 ch,
16-bit
2 ch
28 ch,
16-bit
5 ch
56 ch,
16-bit
10 ch
28 ch
12 ch
28 ch
36 ch
8 ch
28 ch
36 ch
40 KB
32 KB
48 KB
512 KB
CPU
Execution
speed
2
Code Flash
Data Flash
RAM
MPU
ADC (10-bit)
CTU
Total timer
I/O
3
eMIOS
• PWM + MC
+ IC/OC
4
Table 1. MPC5604B/C device comparison
1
(continued)
Device
Feature
MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC5604
02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL BxMG
10 ch
—
20 ch
3 ch
3
5
2
2
6
3
2
5
3
6
2
3
7
1
Yes
45
79
123
45
79
45
79
123
JTAG
64
LQFP
100
LQFP
144
LQFP
64
LQFP
100
LQFP
64
LQFP
100
LQFP
144
LQFP
64
LQFP
100
LQFP
64
LQFP
100
LQFP
144
LQFP
64
LQFP
45
79
45
79
123
45
79
123
Nexus2+
100
208
LQFP MAPBGA
9
3
2
5
40 ch
6 ch
10 ch
—
20 ch
3 ch
10 ch
—
20 ch
3 ch
40 ch
6 ch
10 ch
—
20 ch
3 ch
4
3
6
2
3
7
3
2
5
3
6
10 ch
—
20 ch
3 ch
40 ch
6 ch
10 ch
—
20 ch
3 ch
40 ch
6 ch
Introduction
4
• PWM +
IC/OC
4
• IC/OC
4
SCI (LINFlex)
SPI (DSPI)
MPC5604B/C Microcontroller Data Sheet, Rev. 14
NXP Semiconductor s
CAN
(FlexCAN)
I
2
C
32 kHz
oscillator
GPIO
8
Debug
Package
1
2
3
4
5
6
7
8
9
Feature set dependent on selected peripheral multiplexing—table shows example implementation.
Based on 125 °C ambient operating temperature.
See the eMIOS section of the device reference manual for information on the channel configuration and functions.
IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter.
SCI0, SCI1 and SCI2 are available. SCI3 is not available.
CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
CAN0, CAN3 and either CAN1 or CAN4 are available. CAN2, CAN5 and CAN6 are not available
I/O count based on multiplexing with peripherals.
208 MAPBGA available only as development package for Nexus2+.
Introduction
1.3
Block diagram
SRAM
48 KB
Code Flash Data Flash
512 KB
64 KB
Figure 1
shows a top-level block diagram of the MPC5604B/C device series.
JTAG
JTAG port
Nexus port
Nexus
NMI
SIUL
Voltage
regulator
NMI
Interrupt requests
from peripheral
blocks
INTC
Clocks
FMPLL
CMU
Instructions
e200z0h
(Master)
Data
Nexus 2+
(Master)
64-bit 2 x 3 Crossbar Switch
SRAM
controller
MPU
Flash
controller
(Slave)
(Slave)
(Slave)
MPU
registers
RTC
STM
SWT
ECSM
PIT
MC_RGM MC_CGM MC_ME MC_PCU
BAM
SSCM
Peripheral bridge
Interrupt
request
SIUL
Reset control
External
interrupt
request
IMUX
GPIO and
pad control
36 Ch.
ADC
CTU
2x
eMIOS
4x
LINFlex
3x
DSPI
I
2
C
6x
FlexCAN
WKPU
I/O
Legend:
ADC
BAM
FlexCAN
CMU
CTU
DSPI
eMIOS
FMPLL
I
2
C
IMUX
INTC
JTAG
LINFlex
ECSM
MC_CGM
...
...
...
...
...
Interrupt
request with
wakeup
functionality
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Error Correction Status Module
Clock Generation Module
MC_ME
MC_PCU
MC_RGM
MPU
Nexus
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Mode Entry Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Nexus Development Interface (NDI) Level
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Figure 1. Block diagram
MPC5604B/C Microcontroller Data Sheet, Rev. 14
NXP Semiconductors
5
