MPC850/D
(Motorola Order Number)
1/98
Rev 1
™
Advance Information
MPC850 Integrated Communications Microprocessor
Technical Summary
The MPC850 integrated communications microprocessor is a versatile, one-chip integrated microprocessor
and peripheral combination that can be used in a variety of controller applications, excelling particularly in
communications and networking products. The MPC850, which includes support for Ethernet and
Asynchronous Transfer Mode (ATM), was specifically designed for cost-sensitive remote access, xDSL and
telecom applications. As a low-cost implementation of the MPC860, it provides excellent
price/performance, along with system enhancements such as Universal Serial Bus (USB) support and a
larger dual-port RAM (8KB).
In addition to a high-performance embedded PowerPC core, the MPC850 integrates many system functions
including a versatile memory controller and a communication processor module (CPM) that uses a
specialized, independent RISC processor for communications. This two-processor architecture is more
efficient than traditional architectures because the CPM off-loads peripheral tasks from the embedded
PowerPC core.
The CPM of the MPC850 supports up to seven serial channels — one or two serial communication
controllers (SCCs), one USB channel, two serial management controllers (SMCs), one I
2
C port, and one
serial peripheral interface (SPI). The SCCs are capable of supporting Ethernet, ATM, HDLC and a number
of other protocols, along with a transparent mode of operation. In addition, up to 64 logical HDLC channels
can be supported on a single SCC.
MPC850 Family Members:
MPC850SE
MPC850
MPC850DC
MPC850DE
MPC850DH
MPC850SAR
One SCC supporting only Ethernet; No USB support
One SCC + USB (the SCC supports multiple protocols including Ethernet)
Two SCCs + USB (one SCC supports Ethernet)
Two SCCs + USB (Both SCCs support Ethernet)
Two SCCs + USB (Both SCCs support Ethernet and multichannel HDLC)
Two SCCs + UTOPIA + USB (Both SCCs support Ethernet, multichannel
HDLC and ATM)
To locate any published errata or updates for this document, please refer to our Web site at
http://www.mot.com/SPS/RISC/netcomm.
This document contains information on a new product under development by Motorola.
Motorola reserves the right to change or discontinue this product without notice.
©
Motorola Inc. 1998. All rights reserved.
MPC850 Technical Summary
2-Kbyte
I Cache
Embedded
PowerPC
Core
Instruction
Bus
Instruction
MMU
1-Kbyte
D Cache
Load/Store
Bus
Data
MMU
System Interface Unit
Memory Controller
Unified Bus
Bus Interface Unit
System Functions
Real-time Clock
PCMCIA Interface
Parallel I/O
Baud Rate
Generators
Parallel
Port Pins/
UTOPIA
Four
Timers
Interrupt
Controller
Dual-port
RAM
14 Serial
DMA
Channels
and
2 Virtual
IDMA
Channels
Communication
Processor
Module
32-Bit RISC Microcontroller
and Program ROM
Timer
MAC
Peripheral Bus
USB
SCC2
SCC3
SMC1
SMC2
SPI
I
2
C
Time Slot Assigner
Serial Interface
Figure 1. MPC850 Microprocessor Block Diagram
1.1 Features
The following list summarizes the main features of the MPC850:
•
Embedded PowerPC core with 87 MIPS at 66 MHz (using Dhrystone 2.1)
— Single issue, 32-bit version of the embedded PowerPC core (fully compatible with PowerPC
user instruction set architecture definition) with 32 x 32-bit fixed-point registers
— Power consumption lower than 330 mW (typical) at 33 MHz, 2.2-V internal, 3.3-V I/O
boundary with microprocessor core, caches, memory management, and I/O in operation
— Performs branch folding and branch prediction with conditional prefetch, but without
conditional execution
— 2-Kbyte data cache and 1-Kbyte instruction cache
— Instruction and data caches are two-way, set associative, physical address, 4-word line burst,
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MPC850/MPC850SE Technical Summary
MOTOROLA
least-recently used (LRU) replacement algorithm, lockable on-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— Memory management units support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes,
512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 8 protection groups
•
•
Advanced on-chip emulation debug mode
Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and PowerPC little-endian
memory systems
— Twenty-six external address lines
•
•
Completely static design (0-MHz to 66-MHz operation)
System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— PowerPC decrementer
— PowerPC time base and real-time clock
— Reset controller
— IEEE 1149.1 test access port (JTAG)
•
Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), Flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes, 32 Kbyte to 256 Mbyte
— Selectable write protection
— On-chip bus arbitration supports external bus master
— Special features for burst mode support
•
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
•
Interrupts
— Seven external interrupt request (IRQ) lines
— Eight port pins with interrupt capability
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MPC850/MPC850SE Technical Summary
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— Fourteen internal interrupt sources
— Programmable priority between SCCs
— Programmable highest-priority request
•
Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
•
Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC controller
— Communication specific commands (e.g., graceful stop transmit, close receive buffer
descriptor, RxBD)
— Up to 384 buffer descriptors
— Supports continuous mode transmission and reception on all serial channels
— Up to 8Kbytes of dual-port RAM
— Fourteen serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
•
On-chip 16- x 16-bit multiply-accumulate controller (MAC)
— One operation per clock. Two-clock latency, one-clock blockage.
— MAC operates concurrently with other instructions
— FIR loop: four clocks per four multiplies
•
Four baud rate generators
— Independent and can be connected to any serial communication controller (SCC) or serial
management controller (SMC)
— Allow changes during operation
— Autobaud support option
•
Two SCCs (serial communication controllers)
— QMC microcode for protocol processing of 64 time-division multiplexed channels
— Asynchronous Transfer Mode (ATM)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk™
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
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MPC850/MPC850SE Technical Summary
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•
QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent Tx/Rx buffer descriptors and event/interrupt reporting for each channel
•
ATM support
— Compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis
– (AAL0 support enables OAM and software implementation of other protocols)
— ATM pace control (APC) scheduler, providing:
– Direct support of constant bit rate (CBR)
– Direct support of unspecified bit rate (UBR)
– Control mechanisms enabling software support of available bit rate (ABR)
— Support for two types of physical interfaces
– UTOPIA
– Byte-aligned serial (e.g. T1/E1/ADSL)
— UTOPIA-mode ATM supports:
– UTOPIA level 1 master with cell-level handshake
– Multi-PHY (up to 4 physical layer devices)
– Connection to 25 Mbps, 51 Mbps, or 155 Mbps framers
– UTOPIA clock rates of 1:2 or 1:3 system clock rates
— Serial-mode ATM connection supports:
– Transmission convergence (TC) function for T1/E1/ADSL lines
– Cell delineation
– Cell payload scrambling/descrambling
– Automatic idle/unassigned cell insertion/stripping
– Header error control (HEC) generation, checking, and statistics
– Glueless interface to Motorola CopperGold ADSL transceiver
— Receive VP/VC connection lookup mechanisms, including:
– Internal sequential lookup table supporting up to 32 connections
– Support for up to 64K connections using external memory via address compression or
content-addressable memory (CAM)
— Independent transmit/receive buffer descriptor ring data structures for each connection
— Interrupt report per channel using exception queue
— Supports 53-byte or up to 64-byte (expanded) ATM cells
— AAL5 segmentation and reassembly (SAR) features for segmentation
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MPC850/MPC850SE Technical Summary
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