Freescale Semiconductor, Inc.
Advance Information
MPC852TTS/D
Rev. 1.3, 4/2003
MPC852T PowerQUICC™
Technical Summary
Freescale Semiconductor, Inc...
This document provides an overview of the MPC852T PowerQUICC™ device, describing
major functions and features. The MPC852T PowerQUICC device contains a PowerPC™
processor core.
Topic
Section 1.1, “Features”
Section 1.2, “Embedded MPC8xx Core”
Section 1.3, “System Interface Unit (SIU)”
Section 1.4, “PCMCIA Controller”
Section 1.5, “Power Management”
Section 1.6, “Communications Processor Module (CPM)”
Section 1.7, “Document Revision History”
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The MPC852T PowerQUICC is a 0.18 micron version of the MPC860 PowerQUICC Family
and can operate up to 100 MHz on the MPC8xx Core with a 66 MHz external bus. The
MPC852T has a 1.8 V core and has a 3.3 V I/O operation with 5 V TTL compatibility. The
MPC852T Integrated Communications Controller is a versatile one-chip integrated
microprocessor and peripheral combination that can be used in a variety of controller
applications. It particularly excels in both communications and networking systems.
The MPC852T is a PowerPC architecture-based derivative of Motorola’s MPC860 Quad
Integrated Communications Controller (PowerQUICC). The CPU on the MPC852T is the
MPC8xx core, a 32-bit microprocessor which implements the PowerPC architecture,
incorporating memory management units (MMUs) and instruction and data caches.
Table 1 shows the functionality supported by the MPC852T device:
Table 1. MPC852T
Cache
Part
Instruction
Cache
4 Kbyte
Data Cache
4 Kbyte
Ethernet
10Base
T
Up to 2
SCC
10/100
1
2
No
ATM Support
MPC852T
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Freescale Semiconductor, Inc.
Features
1.1
•
•
Features
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— The 100MHz/80MHz core frequencies support 2:1 mode only
— The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32, 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction cache is two-way, set-associative with 128 sets
– 4-Kbyte data cache is two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory
devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
Fast Ethernet controller (FEC)
General-purpose timers
— Two 16-bit timers or one 32-bit timer
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
System integration unit (SIU)
— Bus monitor
— Software watchdog
MPC852T PowerQUICC™ Technical Summary
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The following list summarizes the key MPC852T features:
•
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•
•
•
•
•
•
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Features
•
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•
•
•
•
•
•
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— 7 port pins with interrupt capability
— 18 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT
MODE
, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— 8 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Two baud rate generators
— Independent (can be connected to SCC3, SCC4 or SMC1)
— Allow changes during operation
— Autobaud support option
Two SCCs (serial communication controllers)
— Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
One SMC (serial management channels)
— UART.
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
PCMCIA interface
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Features
•
•
•
•
— Master (socket) interface, release 2.1 compliant
— Supports one independent PCMCIA sockets. 8 memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: =
≠
< >
— Each watchpoint can generate a break point internally
Normal High and Normal Low Power Modes to conserve power
1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility
256-pin, 23mm x 23mm ball grid array (BGA) package
Table 2. MCPC852T Possible Configurations
HDLC /
Transparent /
UART /
SMC1
Appletalk
(SCC3/SCC4)
Yes
Yes
No
MII=portD, both SCC3 & SCC4 work as
10BaseT; parameter ram reload
microcode needed for SMC1
MII=portD, SCC4 works as 10BaseT while
SCC3 works as HDLC/UART/etc
Freescale Semiconductor, Inc...
No. of
Config
Ethernet
.
Ports
10Base
T
MII
(SCC3/
SCC4)
Yes
Yes
SCC3 &
SCC4
Yes,
SCC4
PCMCI
A
Note
1
3
2
2
Yes
Yes
Yes
Yes, SCC3
The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). The MPC852T block
diagram is shown in Figure 1.
4
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Embedded MPC8xx Core
4-Kbyte
Instruction
Instruction Cache
Bus
System Interface Unit (SIU)
Unified
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
System Functions
PCMCIA-ATA Interface
Embedded
MPC8xx
Processor
Core
Instruction MMU
32-Entry ITLB
Load/Store
Bus
4-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Fast Ethernet
Controller
DMAs
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FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
2 Baud Rate
Generators
2
Interrupt
8-Kbyte
Timers
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
Timers
1 Virtual
IDMA
&
8 Serial
DMA
Channels
MII
SCC3
SCC4
SMC1
SPI
Serial Interface (NMSI)
Figure 1. MPC852T Block Diagram
1.2
Embedded MPC8xx Core
The MPC852T integrates an embedded MPC8xx core with high-performance, low-power peripherals to
extend the
Freescale
data communications family of embedded processors farther into high-end
communications and networking products.
The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC architecture.
It has an integer unit (IU) and a load/store unit (LSU) that execute all integer and load/store operations in
hardware. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware.
The core interface to the internal and external buses is 32 bits.
The IU uses 32, 32-bit GPRs for source and target operands. Typically, it can execute one integer instruction
each clock cycle. Each element in the integer block is clocked only when valid data is in the data queue and
is ready for operation. This holds power consumption of the device to the absolute minimum.
The core is integrated with MMUs as well as instruction and data caches. Each MMU provides a 32-entry,
fully associative instruction and data TLB, with multiple page sizes of 4, 16, 512, and 256 Kbytes and 8
MPC852T PowerQUICC™ Technical Summary
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5
模拟电子
