Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC93H51/D
Rev 2, 2/2004
Low Voltage PLL Clock Driver
The MPC93H51 is a 3.3V compatible, PLL based clock generator
targeted for high performance clock distribution systems. With output
frequencies of up to 240 MHz and a maximum output skew of 150 ps
the MPC93H51 is an ideal solution for the most demanding clock tree
designs. The device offers 9 low skew clock outputs, each is config-
urable to support the clocking needs of the various high-performance
microprocessors including the PowerQuicc II integrated communica-
tion microprocessor. The devices employs a fully differential PLL de-
sign to minimize cycle-to-cycle and long-term jitter.
MPC93H51
LOW VOLTAGE 3.3 V
PLL CLOCK GENERATOR
Features
Freescale Semiconductor, Inc...
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9 outputs LVCMOS PLL clock generator
25 - 240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer
applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
32 lead LQFP package
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
FA SUFFIX
LQFP PACKAGE
CASE 873A-03
Functional Description
The MPC93H51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93H51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL
feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO
frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-4 and
divide-by-8 the internal VCO of the MPC93H51 is running at either 4x or 8x of the reference clock frequency. The
frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO
frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively.
The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential
LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK). The MPC93H51 also provides a static
test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock
is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and
debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs
can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose lock
due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop,
also enabling the PLL to recover to normal operation. The MPC93H51 is 3.3V compatible and requires no external loop
filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS
compatible levels with the capability to drive terminated 50
Ω
transmission lines. For series terminated transmission
lines, each of the MPC93H51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The
device is packaged in a 7x7 mm
2
32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC93H51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes
phase offset between the outputs and the reference signal.
© Motorola, Inc. 2004
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MPC93H51
PCLK
PCLK
TCLK
REF_SEL
EXT_FB
(pullup)
(pulldown)
(pulldown)
(pulldown)
0
1
Ref
PLL
0
1
÷
2
÷
4
÷
8
0
D
1
Q
QA
FB
200–480 MHz
0
D
1
Q
QB
PLL_EN
(pullup)
0
QC0
D
1
QD0
0
D
1
Q
QD1
QD2
QD3
QD4
Q
QC1
Freescale Semiconductor, Inc...
FSELA
FSELB
FSELC
FSELD
(pulldown)
(pulldown)
(pulldown)
(pulldown)
OE
(pulldown)
The MPC93H51 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details.
Figure 1. MPC93H51 Logic Diagram
VCCO
VCCO
GND
GND
17
16
15
14
13
QD2
VCCO
QD3
GND
QD4
VCCO
OE
PCLK
12
11
10
9
1
2
3
4
5
6
7
8
PCLK
QC0
QC1
QD0
QD1
18
GND
24
GND
QB
VCCO
QA
GND
TCLK
PLL_EN
REF_SEL
25
26
27
28
29
30
31
32
23
22
21
20
19
MPC93H51
VCCA
EXT_FB
FSELA
FSELB
FSELC
Figure 2. Pinout: 32-Lead LQFP Package Pinout (Top View)
2
Low Voltage PLL Clock Driver
FSELD
MOTOROLA
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MPC93H51
Table 1. PIN DESCRIPTION
Pin
PCLK, PCLK
TCLK
EXT_FB
REF_SEL
FSELA
FSELB
FSELC
FSELD
OE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Supply
Supply
Supply
I/O
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VCC
VCC
Ground
Function
Differential clock reference
Low voltage positive ECL input
Single ended reference clock signal or test clock
Feedback signal input, connect to a QA, QB, QC, QD output
Selects input reference clock
Output A divider selection
Output B divider selection
Outputs C divider selection
Outputs D divider selection
Output enable/disable
Bank A clock output
Bank B clock output
Bank C clock outputs
Bank D clock outputs1.5
Positive power supply for the PLL
Positive power supply for I/O and core
Negative power supply
Freescale Semiconductor, Inc...
QA
QB
QC0, QC1
QD0 - QD4
VCCA
VCC
GND
Table 2. FUNCTION TABLE
Control
REF_SEL
PLL_EN
OE
FSELA
FSELB
FSELC
FSELD
Default
0
1
0
0
0
0
0
0
Selects PCLK as reference clock
1
Selects TCLK as reference clock
Test mode with PLL disabled. The input clock PLL enabled. The VCO output is routed to the
is directly routed to the output dividers
output dividers
Outputs enabled
QA = VCO
÷
2
QB = VCO
÷
4
QC = VCO
÷
4
QD = VCO
÷
4
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
QA = VCO
÷
4
QB = VCO
÷
8
QC = VCO
÷
8
QD = VCO
÷
8
Table 3. ABSOLUTE MAXIMUM RATINGS
a
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+0.3
V
CC
+0.3
±20
±50
150
Unit
V
V
V
mA
mA
°C
Condition
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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Low Voltage PLL Clock Driver
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MPC93H51
Table 4. GENERAL SPECIFICATIONS
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch-Up
Power Dissipation Capacitance
Input Capacitance
200
2000
200
10
4.0
Min
Typ
V
CC
÷
2
Max
Unit
V
V
V
mA
pF
pF
Per output
Inputs
Condition
Table 5. DC CHARACTERISTICS
(V
CC
= 3.3 V ± 5%, T
A
= 0° to 70°C)
Freescale Semiconductor, Inc...
Symbol
V
IH
V
IL
V
PP
V
CMRa
V
OH
V
OL
Z
OUT
I
IN
I
CCA
I
CCQ
Input High Voltage
Input Low Voltage
Characteristics
Min
2.0
Typ
Max
V
CC
+ 0.3
0.8
Unit
V
V
mV
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
=-24 mA
b
I
OL
= 24 mA
I
OL
= 12 mA
V
IN
= V
CC
or GND
V
CCA
Pin
All V
CC
Pins
Peak-to-Peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output Impedance
Input Leakage Current
Maximum PLL Supply Current
Maximum Quiescent Supply Current
PCLK, PCLK
PCLK, PCLK
250
1.0
2.4
0.55
0.30
7 – 10
±150
6.0
10.0
12.0
14.0
V
CC
-0.6
V
V
V
V
W
µA
mA
mA
a. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range and the
input swing lies within the V
PP
(DC) specification.
b.
The MPC93H51 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
4
Low Voltage PLL Clock Driver
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MPC93H51
Table 6. AC CHARACTERISTICS
(V
CC
= 3.3 V
±
5%, T
A
= 0° to 70°C)
a
Symbol
f
ref
Characteristics
Input Frequency
b
÷
4 feedback
÷
8 feedback
Static test mode
Min
50
25
0
200
÷
2 output
÷
4 output
÷
8 output
100
50
25
25
PCLK, PCLK
PCLK, PCLK
500
1.2
Typ
Max
120
60
300
480
240
120
60
75
1000
V
CC
-0.9
1.0
–150
0
+150
+250
300
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
0.1
50
50
50
55
52.5
51.75
1.0
7.0
6.0
÷
2 feedback
÷
4 feedback
÷
8 feedback
9.0 – 20.0
3.0 – 9.5
1.2 – 2.1
40
25
30
5
Unit
Condition
MHz PLL_EN = 1
MHz PLL_EN = 1
MHz PLL_EN = 0
MHz
MHz
MHz
MHz
%
mV
V
ns
ps
ps
ps
%
%
%
ns
ns
ns
MHz -3 db point of
MHz PLL transfer
characteristic
ps
ps
ps
ms
RMS value
RMS value
RMS value
0.55 to 2.4V
LVPECL
LVPECL
0.8 to 2.0V
PLL locked
PLL locked
f
VCO
f
MAX
VCO Frequency
Maximum Output Frequency
b
f
refDC
V
PP
Reference Input Duty Cycle
Peak-to-Peak Input Voltage
Common Mode Range
TCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
Output-to-Output Skew
Output Duty Cycle
Freescale Semiconductor, Inc...
V
CMRc
tr, tf
d
t
(∅)
t
sk(o)
DC
t
r
, t
f
Output Rise/Fall Time
t
PLZ, HZ
Output Disable Time
t
PZL, ZH
Output Enable Time
BW
PLL closed loop bandwidth
t
JIT(CC)
Cycle-to-cycle jitter
÷
4 feedback
Single Output Frequency Configuration
t
JIT(PER)
Period Jitter
÷
4 feedback
Single Output Frequency Configuration
t
JIT(∅)
t
LOCK
I/O Phase Jitter
Maximum PLL Lock Time
a.
AC characteristics apply for parallel output termination of 50Ω to V
TT
b. The PLL will be unstable with a divide by 2 feedback ratio.
c.
V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the
input swing lies within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts static phase offset t
(∅)
.
d.
The MPC93H51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
(∅)
, can only be guaranteed if tr/tf are
within the specified range.
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Low Voltage PLL Clock Driver
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