MR25H256 / MR25H256A
FEATURES
•
No write delays
•
Unlimited write endurance
•
Data retention greater than 20 years
•
Automatic data protection on power loss
•
Block write protection
•
Fast, simple SPI interface with up to 40 MHz clock rate
•
2.7 to 3.6 Volt power supply range
•
Low current sleep mode
•
Industrial and Automotive Grade 1 and Grade 3 tempera-
tures
•
Available in 8-DFN or 8-DFN Small Flag RoHS-compliant
package.
•
Direct replacement for serial EEPROM, Flash, FeRAM
•
Industrial Grade and AEC-Q100 Grade 1 and Grade 3 options
•
Moisture Sensitivity MSL-3
Product Versions and Options
MR25H256A
has been released for mass production and is recommended for all new designs.
MR25H256
remains in mass production but will be subject to eventual phase out and end of life
and is not recommended for new designs.Both versions have the same specifications.
MR25H256A Product Options
Grade
Industrial
Automotive AEC-Q100 Grade 3
Automotive AEC-Q100 Grade 1
Temperature Package
-40 to +85 C
-40 to +85 C
-40 to +125 C
8-DFN Small Flag
8-DFN Small Flag
8-DFN Small Flag
256Kb Serial SPI MRAM
8-DFN
Small Flag 8-DFN
RoHS
MR25H256 Product Options
(Not recommended for new designs)
Grade
Temperature Package
8-DFN Small Flag
Industrial
-40 to +85 C
8-DFN
Automotive AEC-Q100 Grade 1
-40 to +125 C
8-DFN Small Flag
8-DFN
Copyright © 2017 Everspin Technologies
1
MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................4
Figure 1 – Block Diagram ........................................................................................................................................... 4
System Configuration .....................................................................................................................4
Figure 2 – System Configuration............................................................................................................................. 4
DEVICE PIN ASSIGNMENT ...................................................................................................................5
Figure 3 – Pin Diagram All 8-DFN Packages ........................................................................................................ 5
Table 1 – Pin Functions All 8-DFN Packages ....................................................................................................... 5
SPI COMMUNICATIONS PROTOCOL ...................................................................................................6
Table 2 – Command Codes ....................................................................................................................................... 6
Status Register and Block Write Protection ..................................................................................6
Table 3 – Status Register Bit Assignments ........................................................................................................... 6
Table 4 – Block Memory Write Protection............................................................................................................ 7
Table 5 – Memory Protection Modes .................................................................................................................... 7
Read Status Register (RDSR) ...........................................................................................................7
Figure 4 – RDSR ............................................................................................................................................................. 7
Write Enable (WREN) .......................................................................................................................8
Figure 5 – WREN ............................................................................................................................................................ 8
Write Disable (WRDI) .......................................................................................................................8
Figure 6 – WRDI ............................................................................................................................................................. 8
Write Status Register (WRSR) .........................................................................................................9
Figure 7 – WRSR............................................................................................................................................................. 9
Read Data Bytes (READ) ............................................................................................................... 10
Figure 8 – READ ...........................................................................................................................................................10
Write Data Bytes (WRITE) ............................................................................................................. 11
Figure 9 – WRITE..........................................................................................................................................................11
Enter Sleep Mode (SLEEP) ............................................................................................................ 12
Figure 10 – SLEEP........................................................................................................................................................12
Copyright © 2017 Everspin Technologies
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MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
Table of Contents - Continued
Exit Sleep Mode (WAKE)............................................................................................................... 12
Figure 11 – WAKE ........................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................... 13
Absolute Maximum Ratings ........................................................................................................ 13
Table 6 – Absolute Maximum Ratings.................................................................................................................13
Table 7 – Operating Conditions.............................................................................................................................14
Table 8 – DC Characteristics....................................................................................................................................14
Table 9 – Power Supply Characteristics ..............................................................................................................14
TIMING SPECIFICATIONS ................................................................................................................. 15
Table 10 – Capacitance .............................................................................................................................................15
Table 11 – AC Measurement Conditions ............................................................................................................15
Figure 12 – Output Load for Impedance Parameter Measurements .......................................................15
Figure 13 – Output Load for All Other Parameter Measurements ............................................................15
Power-Up Timing .......................................................................................................................... 16
Table 12 – Power-Up..................................................................................................................................................16
Figure 14 – Power-Up Timing ................................................................................................................................16
Synchronous Data Timing............................................................................................................ 17
Table 13 – AC Timing Parameters .........................................................................................................................17
Figure 15 – Synchronous Data Timing ................................................................................................................19
Figure 16 – HOLD Timing ........................................................................................................................................19
ORDERING INFORMATION ............................................................................................................... 20
Table 14 – Ordering Part Number Decoder Table ...........................................................................................20
Table 15 – Ordering Part Numbers .......................................................................................................................20
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 21
Figure 17 – 8-DFN Small Flag Package................................................................................................................21
Figure 18 – 8-DFN Package .....................................................................................................................................22
REVISION HISTORY ........................................................................................................................... 23
HOW TO REACH US ........................................................................................................................... 24
Copyright © 2017 Everspin Technologies
3
MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
OVERVIEW
The MR25H256/MR25H256A is a serial MRAM with memory array logically organized as 32Kx8 using the four
pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial periph-
eral interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM
and Flash components allowing MRAM to replace these components in the same socket and interoperate
on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating
power, and more reliable data retention compared to available serial memory alternatives.
Figure 1 – Block Diagram
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
32KB
MRAM ARRAY
Instruction Register
Address Register
Counter
SI
15
8
SO
Data I/O Register
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 2 – System Configuration
SCK
MOSI
MISO
SO
SPI
Micro Controller
SI
SCK
SO
SI
SCK
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
CS
CS
1
HOLD
1
CS
2
HOLD
2
HOLD
CS
HOLD
MOSI = Master Out Slave In
MISO = Master In Slave Out
Copyright © 2017 Everspin Technologies
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MR25H256 / MR25H256A Rev. 1.4, 2/2017
MR25H256 / MR25H256A
DEVICE PIN ASSIGNMENT
Figure 3 – Pin Diagram All 8-DFN Packages
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
DD
HOLD
SCK
SI
Top View
Table 1 – Pin Functions All 8-DFN Packages
Signal Name Pin
I/O
Function
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
A low on the write protect input prevents write operations to the Status
Register.
Power supply ground pin.
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
Power supply voltage from +2.7 to +3.6 volts.
CS
1
Input
Chip Select
SO
2
Output
Serial Output
WP
V
SS
SI
3
4
Input
Supply
Write Protect
Ground
5
Input
Serial Input
SCK
6
Input
Serial Clock
HOLD
7
Input
Hold
V
DD
8
Supply
Power Supply
Copyright © 2017 Everspin Technologies
5
MR25H256 / MR25H256A Rev. 1.4, 2/2017
DSP 与 ARM 处理器
