MR20H40 / MR25H40
MR20H40 -
50MHz/20ns
t
SCK (Industrial Temp Range) 4Mb SPI Interface MRAM
MR25H40 -
40MHz/25ns
t
SCK (Industrial, Extended and AEC-Q100 Grade 1 Temp Range) 4Mb SPI Interface MRAM
For more information on product options, see
“Table 16 – Ordering Part Numbers” on page 25.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
No write delays
Unlimited write endurance
Data retention greater than 20 years
Automatic data protection on power loss
Fast, simple SPI interface, up to 50 MHz clock rate with MR20H40.
3.0 to 3.6 Volt power supply range
Low-current sleep mode
Industrial (-40 to 85°C), Extended (-40 to 105°C), and AEC-Q100
Grade 1 (-40 to 125°C) temperature range options.
Available in 8-pin DFN or 8-pin DFN Small Flag, RoHS-compliant
packages.
Direct replacement for serial EEPROM, Flash, and FeRAM
MSL Level 3
8-DFN Small Flag
8-DFN
RoHS
DESCRIPTION
MR2xH40 is a family of 4,194,304-bit magnetoresistive random access memory (MRAM) devices
organized as 524,288 words of 8 bits. They are the ideal memory solution for applications that must
store and retrieve data and programs quickly using a small number of I/O pins. They have serial EE-
PROM and serial Flash compatible read/write timing with no write delays and unlimited read/write
endurance. Unlike other serial memories, with the MR2xH40 family both reads and writes can occur
randomly in memory with no delay between writes.
The MR2xH40 family provides highly reliable data storage over a wide range of temperatures. The
MR20H40 (50MHz) is offered with Industrial (-40° to +85 °C) range. The MR25H40 (40MHz) is offered
with Industrial (-40° to +85 °C), Extended (-40 to 105°C), and AEC-Q100 Grade 1 (-40°C to +125 °C)
operating temperature range options.
Both are available in a 5 x 6mm, 8-pin DFN package. The pinout is compatible with serial SRAM,
EEPROM, Flash, and FeRAM products.
Copyright © Everspin Technologies 2018
1
MR20H40 / MR25H40 Revision 12.4, 3/2018
MR20H40 / MR25H40
TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................5
Figure 1 – Block Diagram ........................................................................................................................................... 5
System Configuration .....................................................................................................................5
Figure 2 – System Configuration............................................................................................................................. 5
Pin Functions ...................................................................................................................................6
Figure 3 – DFN Package Pin Diagram (Top View) .............................................................................................. 6
Table 1 – Pin Functions ............................................................................................................................................... 6
SPI COMMUNICATIONS PROTOCOL ...................................................................................................7
Command Codes..............................................................................................................................7
Table 2 – Command Codes ....................................................................................................................................... 7
Status Register, Memory Protection and Block Write Protection ................................................8
Table 3 – Status Register Bit Assignments ........................................................................................................... 8
Memory Protection Modes .............................................................................................................8
Table 4 – Memory Protection Modes .................................................................................................................... 8
Block Protection Modes ..................................................................................................................9
Table 5 – Block Memory Write Protection............................................................................................................ 9
Read Status Register (RDSR) ........................................................................................................ 10
Figure 4 – Read Status Register (RDSR) Timing ................................................................................................10
Write Enable (WREN) .................................................................................................................... 10
Figure 5 – Write Enable (WREN) Timing ..............................................................................................................10
Write Disable (WRDI) .................................................................................................................... 11
Figure 6 – Write Disable (WRDI) Timing ..............................................................................................................11
Write Status Register (WRSR) ...................................................................................................... 11
Figure 7 – Write Status Register (WRSR) Timing ..............................................................................................11
Read Data Bytes (READ) ............................................................................................................... 12
Figure 8 – Read Data Bytes (READ) Timing ........................................................................................................12
Copyright © Everspin Technologies 2018
2
MR20H40 / MR25H40 Revision 12.4 3/2018
MR20H40 / MR25H40
Table of Contents (Cont’d)
Write Data Bytes (WRITE) ............................................................................................................. 12
Figure 9 – Write Data Bytes (WRITE) Timing ......................................................................................................13
Enter Sleep Mode (SLEEP) ............................................................................................................ 13
Figure 10 – Enter Sleep Mode (SLEEP) Timing..................................................................................................13
Exit Sleep Mode (WAKE)............................................................................................................... 14
Figure 11 – Exit Sleep Mode (WAKE) Timing .....................................................................................................14
ELECTRICAL SPECIFICATIONS ......................................................................................................... 15
Absolute Maximum Ratings ........................................................................................................ 15
Table 6 – Absolute Maximum Ratings ..............................................................................................................15
Table 7 – Operating Conditions.............................................................................................................................16
Table 8 – DC Characteristics....................................................................................................................................16
Table 9 – Power Supply Characteristics ..............................................................................................................17
TIMING SPECIFICATIONS ................................................................................................................. 18
Capacitance................................................................................................................................... 18
Table 10 – Capacitance .............................................................................................................................................18
AC Measurement Conditions ....................................................................................................... 18
Table 11 – AC Measurement Conditions ............................................................................................................18
Figure 12 – Output Load for Impedance Parameter Measurements .......................................................18
Figure 13 – Output Load for all Other Parameter Measurements.............................................................18
Power Up Timing .......................................................................................................................... 19
Table 12 – Power-Up Timing ...................................................................................................................................19
Figure 14 – Power-Up Timing ................................................................................................................................19
AC Timing Parameters .................................................................................................................. 20
Table 13 – MR20H40 (
f
SCK = 50MHz) AC Timing Parameters .....................................................................20
Table 14 – MR25H40 (
f
SCK = 40MHz) AC Timing Parameters .....................................................................21
Copyright © Everspin Technologies 2018
3
MR20H40 / MR25H40 Revision 12.4, 3/2018
MR20H40 / MR25H40
Table of Contents (Cont’d)
Figure 15 – Synchronous Data Timing ................................................................................................................23
Figure 16 – HOLD Timing ........................................................................................................................................23
PART NUMBERS AND ORDERING .................................................................................................... 24
Table 15 – Part Numbering System ......................................................................................................................24
Table 16 – Ordering Part Numbers .......................................................................................................................25
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 26
Figure 17 – DFN Package Outline ........................................................................................................................26
Figure 18 – DFN Small Flag Package....................................................................................................................27
REVISION HISTORY ........................................................................................................................... 28
HOW TO REACH US ........................................................................................................................... 29
Copyright © Everspin Technologies 2018
4
MR20H40 / MR25H40 Revision 12.4 3/2018
MR20H40 / MR25H40
OVERVIEW
The MR2xH40 family is an SPI interface MRAM family with a memory array logically organized as 512Kx8
using the four pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the
serial peripheral interface (SPI) bus. The MRAM implements a subset of commands common to SPI EEPROM
and SPI Flash components. This allows the SPI MRAM to replace these components in the same socket
and interoperate on a shared SPI bus. The SPI MRAM offers superior write speed, unlimited endurance, low
standby & operating power, and simple, reliable data retention compared to other serial memory alterna-
tives.
Figure 1 – Block Diagram
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
512Kb x 8
MRAM ARRAY
Instruction Register
Address Register
Counter
SI
19
8
SO
Data I/O Register
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 2 – System Configuration
SCK
MOSI
MISO
SO
SPI
Micro Controller
SI
SCK
SO
SI
SCK
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
CS
CS
1
HOLD
1
CS
2
HOLD
2
HOLD
CS
HOLD
MOSI = Master Out Slave In
MISO = Master In Slave Out
Copyright © Everspin Technologies 2018
5
MR20H40 / MR25H40 Revision 12.4, 3/2018
ADI参考电路
